HI5780-EV Ver la hoja de datos (PDF) - Intersil
Número de pieza
componentes Descripción
Lista de partido
HI5780-EV Datasheet PDF : 8 Pages
| |||
HI5780
Absolute Maximum Ratings
Thermal Information
Supply Voltage VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Digital Input Voltages (D9-D0, CLK, BLANK, PD) . . . . VDD to -0.5V
Internal Reference Output Current . . . . . . . . . . . . . . . . . . . . ±2.5mA
Reference Input Voltage Range (VREF) . . . . . . . . . . . . VDD to -0.5 V
Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA
Operating Conditions
Temperature Range, HI5780BIx . . . . . . . . . . . . . . . . . -20oC to 75oC
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
122
Maximum Junction Temperature (Plastic Package)
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(MQFP - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications AVDD, DVDD = 5.00V, VREF = 2.0V, fCLK = 80 MSPS, RLOAD = 200Ω, RREF = 3.3kΩ,
TA = 25oC
HI5780JCQ
PARAMETER
TEST CONDITIONS
MIN TYP MAX
SYSTEM PERFORMANCE
Resolution
10
-
-
Integral Linearity Error, INL
(Notes 4, 5) (“Best Fit” Straight Line)
-2.0 1.25
2.0
Differential Linearity Error, DNL
(Notes 4, 5)
-0.5 0.25
0.5
Offset Error, IOS
Full Scale Output Current, IFS
Full Scale Drift Coefficient, IDRIFT
Output Voltage Compliance Range
(Notes 4, 5)
(Note 4)
(Note 2)
(Note 3), 10-Bit Accuracy
-
-
5
9.0 9.6
10
-
0.26
-
1.8 1.92 2.0
DYNAMIC CHARACTERISTICS
Throughput Rate
(Note 3)
80.0
-
-
Output Voltage Full Scale Step
Settling Time, tSETT FS
Singlet Glitch Area, GE (Peak)
Differential Gain, DG
To ±0.5 LSB Error Band RL = 75Ω, 10-Bit Accuracy
-
6.0
-
(Note 3)
RLOAD = 75Ω, VOUT = 1.0VP-P (Note 3)
(Note 4)
-
40
-
-
2.5
-
Differential Phase, DP
(Note 4)
-
1.3
-
Spurious Free Dynamic Range,
SFDR to Nyquist
fCLK = 40 MSPS, fOUT = 2.02MHz, 20MHz Span
(Note 3)
-
48.5
-
fCLK = 80 MSPS, fOUT = 2.02MHz, 40MHz Span
(Note 3)
-
47.5
-
fCLK = 40 MSPS, fOUT = 10MHz, 20MHz Span (Note 3) - 40.75
-
fCLK = 80 MSPS, fOUT = 20MHz, 40MHz Span (Note 3) -
38.5
-
Spurious Free Dynamic Range, SFDR Within fCLK = 40 MSPS, fOUT = 2.02MHz, 2MHz Span (Note 3) -
75.0
-
a Window
fCLK = 80 MSPS, fOUT = 2.02MHz, 2MHz Span (Note 3) -
73.5
-
fCLK = 40 MSPS, fOUT = 10MHz, 2MHz Span (Note 3) -
56.5
-
fCLK = 80 MSPS, fOUT = 20MHz, 2MHz Span (Note 3) -
49.0
-
REFERENCE
Internal Reference Voltage, REFOUT
Internal Reference Voltage Drift
(Notes 4, 5)
(Note 3)
1.0 1.25 1.3
-
0.34
-
Reference Input Voltage Range, VREF
(Note 3)
0.5
-
2.0
UNITS
Bits
LSB
LSB
µA
mA
mV/oC
V
MSPS
ns
pV-s
%
Degrees
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
V
mV/oC
V
10-1718
Share Link: 