HIP6004D Ver la hoja de datos (PDF) - Intersil
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HIP6004D Datasheet PDF : 14 Pages
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HIP6004D
TABLE 1. OUTPUT VOLTAGE PROGRAM
VID4
PIN NAME
VID3 VID2 VID1
VID0
NOMINAL OUTPUT
VOLTAGE DACOUT
VID4
PIN NAME
VID3 VID2 VID1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
0
1.100
0
1
1
1
1
1
1
0
1
1.125
0
1
1
0
1
1
1
0
0
1.150
0
1
1
0
1
1
0
1
1
1.175
0
1
0
1
1
1
0
1
0
1.200
0
1
0
1
1
1
0
0
1
1.225
0
1
0
0
1
1
0
0
0
1.250
0
1
0
0
1
0
1
1
1
1.275
0
0
1
1
1
0
1
1
0
1.300
0
0
1
1
1
0
1
0
1
1.325
0
0
1
0
1
0
1
0
0
1.350
0
0
1
0
1
0
0
1
1
1.375
0
0
0
1
1
0
0
1
0
1.400
0
0
0
1
1
0
0
0
1
1.425
0
0
0
0
1
0
0
0
0
1.450
0
0
0
0
NOTE: 0 = connected to GND or VSS, 1 = connected to VDD through pull-up resistors.
VID0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
NOMINAL OUTPUT
VOLTAGE DACOUT
1.475
1.500
1.525
1.550
1.575
1.600
1.625
1.650
1.675
1.700
1.725
1.750
1.775
1.800
1.825
1.850
VIN
HIP6004D
UGATE
PHASE
LGATE
PGND
Q1
LO
VOUT
Q2
D2
CIN CO
RETURN
FIGURE 5. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
Figure 5 shows the critical power components of the converter.
To minimize the voltage overshoot the interconnecting wires
indicated by heavy lines should be part of ground or power
plane in a printed circuit board. The components shown in
Figure 5 should be located as close together as possible.
Please note that the capacitors CIN and CO each represent
numerous physical capacitors. Locate the HIP6004D within 3
inches of the MOSFETs, Q1 and Q2. The circuit traces for the
MOSFETs’ gate and source connections from the HIP6004D
must be sized to handle up to 1A peak current.
Figure 6 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS pin and locate the capacitor, CSS
close to the SS pin because the internal current source is
only 10μA. Provide local VCC decoupling between VCC and
GND pins. Locate the capacitor, CBOOT as close as
practical to the BOOT and PHASE pins.
BOOT
D1
CBOOT
PHASE
HIP6004D
SS
VCC +12V
+VIN
Q1 LO
Q2
CO
VOUT
CSS
GND
CVCC
FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
Feedback Compensation
Figure 7 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(VOUT) is regulated to the Reference voltage level. The
error amplifier (Error Amp) output (VE/A) is compared with
the oscillator (OSC) triangular wave to provide a pulse-
width modulated (PWM) wave with an amplitude of VIN at
the PHASE node.
8
FN4855.3
July 13, 2005
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