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HIP6018B
(Rev.:1999)

Advanced PWM and Dual Linear Power Control

Intersil 

HIP6018B

Description

Operation

The HIP6018B monitors and precisely controls 4 output

voltage levels (Refer to Figures 1, 2, and 3). It is designed for

microprocessor computer applications with 3.3V and 5V

power, and 12V bias input from an ATX power supply. The IC

has one PWM controller, a linear controller, and a linear

regulator. The PWM controller is designed to regulate the

microprocessor core voltage (VOUT1) by driving 2 MOSFETs

(Q1 and Q2) in a synchronous-rectified buck converter

configuration. The core voltage is regulated to a level

programmed by the 5-bit digital-to-analog converter (DAC).

An integrated linear regulator supplies the 2.5V clock power

(VOUT2). The linear controller drives an external MOSFET

(Q3) to supply the GTL bus power (VOUT3).

Initialization

The HIP6018B automatically initializes upon receipt of input

power. Special sequencing of the input supplies is not

necessary. The Power-On Reset (POR) function continually

monitors the input supply voltages. The POR monitors the

bias voltage (+12VIN) at the VCC pin, the 5V input voltage

(+5VIN) on the OCSET1 pin, and the 3.3V input on the VIN2

pin. The normal level on OCSET1 is equal to +5VIN less a

fixed voltage drop (see over-current protection). The POR

function initiates soft-start operation after all three input supply

voltages exceed their POR thresholds.

Soft-Start

The POR function initiates the soft-start sequence. Initially,

the voltage on the SS pin rapidly increases to approximately

1V (this minimizes the soft-start interval). Then an internal

11µA current source charges an external capacitor (CSS) on

the SS pin to 4V. The PWM error amplifier reference input

(+terminal) and output (COMP1 pin) is clamped to a level

proportional to the SS pin voltage. As the SS pin voltage

slews from 1V to 4V, the output clamp generates PHASE

pulses of increasing width that charge the output

capacitor(s). After this initial stage, the reference input clamp

slows the output voltage rate-of-rise and provides a smooth

transition to the final set voltage. Additionally both linear

regulator’s reference inputs are clamped to a voltage

proportional to the SS pin voltage. This method provides a

rapid and controlled output voltage rise.

Figure 3 shows the soft-start sequence for the typical

application. At T0 the SS voltage rapidly increases to

approximately 1V. At T1, the SS pin and error amplifier

output voltage reach the valley of the oscillator’s triangle

wave. The oscillator’s triangular waveform is compared to

the clamped error amplifier output voltage. As the SS pin

voltage increases, the pulse-width on the PHASE pin

increases. The interval of increasing pulse-width continues

until each output reaches sufficient voltage to transfer

control to the input reference clamp. If we consider the 2.0V

output (VOUT1) in Figure 3, this time occurs at T2. During

the interval between T2 and T3, the error amplifier

reference ramps to the final value and the converter

regulates the output to a voltage proportional to the SS pin

voltage. At T3 the input clamp voltage exceeds the

reference voltage and the output voltage is in regulation.

PGOOD

(2V/DIV)

0V

SOFT-START

(1V/DIV)

0V

OUTPUT

VOLTAGES

(0.5V/DIV)

VOUT2 ( = 2.5V)

VOUT1 (DAC = 2V)

VOUT3 ( = 1.5V)

0V

T0 T1

T2

T3

T4

TIME

FIGURE 6. SOFT-START INTERVAL

The remaining outputs are also programmed to follow the SS

pin voltage. Each linear output (VOUT2 and VOUT3) initially

follows a ramp similar to that of the PWM output. When each

output reaches sufficient voltage the input reference clamp

slows the rate of output voltage rise. The PGOOD signal

toggles ‘high’ when all output voltage levels have exceeded

their under-voltage levels. See the Soft-Start Interval section

under Applications Guidelines for a procedure to determine

the soft-start interval.

Fault Protection

All three outputs are monitored and protected against

extreme overload. A sustained overload on any linear

regulator output or an over-voltage on the PWM output

disables all converters and drives the FAULT pin to VCC.

Figure 7 shows a simplified schematic of the fault logic. An

over-voltage detected on VSEN1 immediately sets the fault

latch. A sequence of three over-current fault signals also sets

the fault latch. A comparator indicates when CSS is fully

charged (UP signal), such that an under-voltage event on

either linear output (FB2 or FB3) is ignored until after the soft-

start interval (T4 in Figure 6). At startup, this allows VOUT2

and VOUT3 to slew up over increased time intervals, without

generating a fault. Cycling the bias input voltage (+12VIN on

the VCC pin) off then on resets the counter and the fault latch.

2-244

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