HMN1288D-70 Ver la hoja de datos (PDF) - Unspecified

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HMN1288D-70

Non-Volatile SRAM MODULE 1Mbit (128K x8-Bit), 32Pin-DIP, 5V

Unspecified 

HANBit

HMN1288D

POWER-DOWN/POWER-UP CYCLE (TA= TOPR, VCC=5V)

PARAMETER

SYMBOL

CONDITIONS

MIN

VCC slew, 4.75 to 4.25V

tPF

300

VCC slew, 4.75 to VSO

tFS

10

VCC slew, VSO to VPFD (max)

tPU

0

Chip enable recovery time

Data-retention time in

Absence of VCC

Write-protect time

Time during which SRAM

tCER

is write-protected after VCC

40

passes VPFD on power-up.

tDR

TA = 25℃

10

Delay after VCC slew’s down

tWPT

past VPFD before SRAM is

40

Write-protected.

TYP.

-

-

-

80

-

100

MAX

-

-

-

120

-

150

UNIT

㎲

㎲

㎲

ms

years

㎲

TIMING WAVEFORM

- READ CYCLE NO.1 (Address Access)*1,2

Address

DOUT

tRC

tACC

tOH

Previous Data Valid

Data Valid

- READ CYCLE NO.2 (/CE Access)*1,3,4

tRC

CE

DOUT

tACE

tCLZ

High-Z

tCHZ

High-Z

URL : www.hbe.co.kr

Rev. 1.0 (June, 2002)

6

HANBit Electronics Co.,Ltd

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