HMP8115CN Ver la hoja de datos (PDF) - Intersil
Número de pieza
componentes Descripción
Lista de partido
HMP8115CN Datasheet PDF : 43 Pages
| |||
HMP8115
NTSC M
PAL B, D, G, H, I, N, NC
LINES 1 - 22 NOT ACTIVE
240 ACTIVE LINES
PER FIELD
(LINES 23-262)
480 ACTIVE
LINES / FRAME
(NTSC, PAL M) LINES 263 - 284 NOT ACTIVE
ODD FIELD
SYNC AND
BACK
PORCH
VERTICAL
BLANKING
EVEN FIELD
LINES 1 - 22 NOT ACTIVE
288 ACTIVE LINES
PER FIELD
(LINES 23 - 310)
LINES 311 - 335 NOT ACTIVE
576 ACTIVE
LINES / FRAME
(PAL)
240 ACTIVE LINES
PER FIELD
(LINES 285 - 524)
LINE 525
NOT ACTIVE
FRONT
PORCH
NUMBER OF PIXELS
RECTANGULAR (SQUARE)
NTSC
PAL
288 ACTIVE LINES
PER FIELD
(LINES 336 - 623)
LINES 624-625
NOT ACTIVE
NOTE:
TOTAL PIXELS
ACTIVE PIXELS
858 (780)
720 (640)
864 (944)
720 (768)
TOTAL PIXELS
ACTIVE PIXELS
7. The line numbering for PAL (M) followings NTSC (M) line count minus 3 per the video standards.
FIGURE 9. TYPICAL ACTIVE VIDEO REGIONS
PIN NAME
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
8-BIT, 4:2:2, YCbCr
0
0
0
0
0
0
0
0
Y0, Cb0, Cr0
Y1, Cb1, Cr1
Y2, Cb2, Cr2
Y3, Cb3, Cr3
Y4, Cb4, Cr4
Y5, Cb5, Cr5
Y6, Cb6, Cr6
Y7, Cb7, Cr7
TABLE 3. PIXEL OUTPUT FORMATS
16-BIT, 4:2:2, YCbCr 15-BIT, RGB, (5,5,5)
Cb0, Cr0
B0
Cb1, Cr1
B1
Cb2, Cr2
B2
Cb3, Cr3
B3
Cb4, Cr4
B4
Cb5, Cr5
G0
Cb6, Cr6
G1
Cb7, Cr7
G2
Y0
G3
Y1
G4
Y2
R0
Y3
R1
Y4
R2
Y5
R3
Y6
R4
Y7
0
16-BIT, RGB, (5,6,5)
B0
B1
B2
B3
B4
G0
G1
G2
G3
G4
G5
R0
R1
R2
R3
R4
BT.656
0
0
0
0
0
0
0
0
YCbCr Data,
Ancillary Data,
SAV and EAV
Sequences
PIXEL OUTPUT PORT
Pixel data is output via the P0-P15 pins. Refer to Table 3 for
the output pin definition as a function of the output mode.
8-BIT YCbCr OUTPUT
The DVALID output pin may be configured to operate in one
of two ways. The configuration is determined by the
DVLD_LTC bit (bit 4) of the GENLOCK CONTROL register
04H.
If DVLD_LTC=0, the DVALID output is continuously asserted
during the entire active video time on active scan lines if CLK2
is exactly 2x the desired output sample rate. DVALID being
asserted indicates valid pixel data is present on the P15-P8
pixel outputs. DVALID is never asserted during the blanking
intervals. Refer to Figure 10.
If DLVD_LTC=1, DVALID has the same internal timing as the
first mode, but is ANDed with the CLK2 signal, and the result
is output onto the DVALID pin. This results in a gated CLK2
signal being output during the active video time on active
scan lines. Refer to Figure 11.
If 8-bit YCbCr data is generated, it is output following each
rising edge of CLK2. The YCbCr data is multiplexed as [Cb Y
Cr Y′ Cb Y Cr Y′...], with the first active data each scan line
containing Cb data. The pixel output timing is shown in Fig-
ures 10 and 11.
BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD
are output following the rising edge of CLK2. When BLANK
is asserted and VBIVALID is deasserted, the YCbCr outputs
have a value of 16 for Y and 128 for Cb and Cr.
11
Share Link: 