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HSP50214BVC

Programmable Downconverter

Intersil 

HSP50214B

Typically, the average input error is read from the Input Level

Detector port for use in AGC Applications. By setting the

threshold to 0, however, the average value of the input signal

can be read directly. The calculation is:

dBFSRMS = (20)log[(1.111)(level) ⁄ ((N)(16))]

(EQ. 2)

where “level” is the 24-bit value read from the 3 level

Detector Registers and “N” is the number of samples to be

integrated. Note that to get the RMS value of a sinusoid,

multiply the average value of the rectified sinusoid by 1.111.

For a full scale input sinusoid, this yields an RMS value of

approximately 3dBfS.

NOTE: 1.111 scales the rectified sinusoid average (2/π) to 1/ √2

.

A) INPUT SIGNAL

B) RECTIFIED SIGNAL

C) THRESHOLD

D) ACCUMULATOR INPUTS

E) DETECTOR OUTPUT

F) CLOSED LOOP STEADY STATE

(CONSTANT INPUT)

FIGURE 11. SIGNAL PROCESSING WITHIN LEVEL DETECTOR

In the HSP50214B, the polarity of the LSB’s of the

integration period pre-load is selectable. If Control Word 27,

Bit 23 is set to a logic one, the two LSB’s of the integration

period preload are set to logic ones. This allows a power of

two to be set for the integration period, for easy

normalization in the processor. If Control Word 27, Bit 23 is

set to a logic zero, then the two LSB’s of the integration

period preload are set to zeros as in the HSP50214.

Carrier Synthesizer/Mixer

The Carrier Synthesizer/Mixer Section of the HSP50214B is

shown in Figure 12. The NCO has a 32-bit phase

accumulator, a 10-bit phase offset adder, and a sine/cosine

ROM. The frequency of the NCO is the sum of a center

frequency Control Word, loaded via the microprocessor

interface (Control Word 3, Bits 0 to 31), and an offset

frequency, loaded serially via the COF and COFSYNC pins.

The offset frequency can be zeroed in Control Word 0, Bit 1.

Both frequency control terms are 32-bits and the addition is

modulo 232. The output frequency of the NCO is computed

as:

fC = fS* N ⁄ (232) ,

(EQ. 3)

or in terms of the programmed value:

N = INT[fC × 232 ⁄ fS]HEX ,

(EQ. 3A)

where N is the 32-bit sum of the center and offset frequency

terms, fC is the frequency of the carrier NCO sinusoids, fS is

the input sampling frequency, and INT is the integer of the

computation. See the Microprocessor Write Section on

instructions for writing Control Word 3.

TO MIXERS

COS

SIN

18 18

REG

REG

SIN/COS

ROM

CARRIER

PHASE

STROBE†

18

10 R R

+

EE

GG

CARRIER

PHASE

OFFSET †

PHASE

ACCUMULATOR

ENI

REG

0

R

MUX

E

G

CLEAR

PHASE

ACCUM †

COF

ENABLE †

MUX

32

COF

0

REG

+

32

CF

CARRIER

FREQUENCY

STROBE †

COFSYNC

COF

SYNCIN1

SYNC

SHIFT REG

SYNC

CIRCUITRY

REG

REG

CARRIER

FREQUENCY†

(fC)

CARRIER

LOAD ON

UPDATE†

† Controlled via microprocessor interface.

FIGURE 12. BLOCK DIAGRAM OF NCO SECTION

For example, if N is 3267 (decimal), and fS is 65MHz, then fC

is 49.44Hz. If received data is modulated at a carrier

frequency of 10MHz, then the synthesizer/mixer should be

programmed for N = 27627627 (hex) or D89D89D8 (hex).

Because the input enable, ENI, controls the operation of the

phase accumulator, the NCO output frequency is computed

relative to the input sample rate, fS, not to fCLKIN. The

frequency control, N, is interpreted as two’s complement

because the output of the NCO is quadrature. Negative

frequency L.O.s select the upper sideband; positive frequency

L.O.s select the lower sideband. The range of the NCO is

-fS /2 to +fS /2. The frequency resolution of the NCO is fS /(232)

or approximately 0.015Hz when CLKIN is 65MSPS and ENI is

tied low.

13

FN4450.4

May 1, 2007

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