HT1647A(2009) Ver la hoja de datos (PDF) - Holtek Semiconductor
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HT1647A Datasheet PDF : 19 Pages
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PATENTED
VDD
V LC D
R
V1
R
V2
R
V3
R
V4
R
VSS
1 /5 b ia s
*V R
*V L C D
VDD
V LC D
R
V1
R
V2
R
V3
R
V4
R
VSS
1 /4 b ia s
*V R
*V L C D
* T h e v o lta g e a p p lie d to V L C D p in m u s t b e lo w e r th a n V D D
* A d ju s t V R to fit L C D d is p la y , a t V D D = 5 V , V L C D = 4 V , V R = 1 5 k W ± 2 0 %
Internal Resistor Type Bias Generator Configurations
HT1647A
Interfacing
Only six lines are required to interface with the
HT1647A. The CS line is used to initialize the serial in-
terface circuit and to terminate the communication be-
tween the host controller and the HT1647A. If the CS pin
is set to 1, the data and command issued between the
host controller and the HT1647A are first disabled and
then initialized. Before issuing a mode command or
mode switching, a high level pulse is required to initial-
ize the serial interface of the HT1647A. The DB0~DB3
are the 4-bit parallel data input/output lines. Data to be
read or written or commands to be written have to pass
through the DB0~DB3 lines. The RD line is the READ
clock input. Data in the RAM are clocked out on the fall-
ing edge of the RD signal, and the clocked out data will
then appear on the DB0~DB3 lines. It is recommended
that the host controller read correct data during the inter-
val between the rising edge and the next falling edge of
the RD signal. The WR line is the WRITE clock input. The
data, address, and command on the DB0~DB3 lines are
all clocked into the HT1647A on the rising edge of the
WR signal. There is an optional IRQ line to be used as an
interface between the host controller and the HT1647A.
The IRQ pin can be selected as a timer output or a WDT
overflow flag output by the S/W setting. The host con-
troller can perform the time base or the WDT function by
connecting with the IRQ pin of the HT1647A.
Rev. 1.20
13
June 22, 2009
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