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HT46R62

A/D with LCD Type 8-Bit MCU

Holtek Semiconductor 

HT46R62/HT46C62

Once an interrupt subroutine is serviced, other inter-

rupts are all blocked (by clearing the EMI bit). This

scheme may prevent any further interrupt nesting. Other

interrupt requests may take place during this interval,

but only the interrupt request flag will be recorded. If a

certain interrupt requires servicing within the service

routine, the EMI bit and the corresponding bit of the

INTC0 or of INTC1 may be set in order to allow interrupt

nesting. Once the stack is full, the interrupt request will

not be acknowledged, even if the related interrupt is en-

abled, until the SP is decremented. If immediate service

is desired, the stack should be prevented from becom-

ing full.

All these interrupts can support a wake-up function. As

an interrupt is serviced, a control transfer occurs by

pushing the contents of the program counter onto the

stack followed by a branch to a subroutine at the speci-

fied location in the ROM. Only the contents of the pro-

gram counter is pushed onto the stack. If the contents of

the register or of the status register (STATUS) is altered

by the interrupt service program which corrupts the de-

sired control sequence, the contents should be saved in

advance.

External interrupts are triggered by a an edge transition

of INT0 or INT1 (option: high to low, low to high, low to

high or high to low), and the related interrupt request flag

(EIF0; bit 4 of INTC0, EIF1; bit 5 of INTC0) is set as well.

After the interrupt is enabled, the stack is not full, and

the external interrupt is active, a subroutine call to loca-

tion 04H or 08H occurs. The interrupt request flag (EIF0

or EIF1) and EMI bits are all cleared to disable other

maskable interrupts.

The internal Timer/Event Counter interrupt is initialized

by setting the Timer/Event Counter interrupt request flag

(TF; bit 6 of INTC0), which is normally caused by a timer

overflow. After the interrupt is enabled, and the stack is

not full, and the TF bit is set, a subroutine call to location

0CH occurs. The related interrupt request flag (TF) is re-

set, and the EMI bit is cleared to disable further interrupts.

The time base interrupt is initialized by setting the time

base interrupt request flag (TBF; bit 5 of INTC1), that is

caused by a regular time base signal. After the interrupt

is enabled, and the stack is not full, and the TBF bit is

set, a subroutine call to location 14H occurs. The related

interrupt request flag (TBF) is reset and the EMI bit is

cleared to disable further maskable interrupts.

The real time clock interrupt is initialized by setting the

real time clock interrupt request flag (RTF; bit 6 of

INTC1), that is caused by a regular real time clock sig-

nal. After the interrupt is enabled, and the stack is not

full, and the RTF bit is set, a subroutine call to location

18H occurs. The related interrupt request flag (RTF) is

reset and the EMI bit is cleared to disable further inter-

rupts.

During the execution of an interrupt subroutine, other in-

terrupt acknowledgments are all held until the ²RETI²

instruction is executed or the EMI bit and the related in-

Bit No.

0

1

2

3

4

5

6

7

Label

EMI

EEI0

EEI1

ETI

EIF0

EIF1

TF

¾

Function

Control the master (global) interrupt (1=enabled; 0=disabled)

Control the external interrupt 0 (1=enabled; 0=disabled)

Control the external interrupt 1 (1=enabled; 0=disabled)

Control the Timer/Event Counter interrupt (1=enabled; 0=disabled)

External interrupt 0 request flag (1=active; 0=inactive)

External interrupt 1 request flag (1=active; 0=inactive)

Internal Timer/Event Counter request flag (1=enable; 0=disable)

For test mode used only.

Must be written as ²0²; otherwise may result in unpredictable operation.

INTC0 (0BH) Register

Bit No.

0

1

2

3, 4

5

6

7

Rev. 1.60

Label

¾

ETBI

ERTI

¾

TBF

RTF

¾

Function

Unused bit, read as ²0²

Control the time base interrupt (1=enabled; 0:disabled)

Control the real time clock interrupt (1=enabled; 0:disabled)

Unused bit, read as ²0²

Time base request flag (1=active; 0=inactive)

Real time clock request flag (1=active; 0=inactive)

Unused bit, read as ²0²

INTC1 (1EH) Register

11

July 14, 2005

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