HT46R652 Ver la hoja de datos (PDF) - Holtek Semiconductor

Número de pieza

componentes Descripción

Lista de partido

HT46R652

A/D with LCD Type 8-Bit OTP MCU

Holtek Semiconductor 

HT46R652

Indirect Addressing Register

Locations 00H and 02H are for indirect addressing reg-

isters that are not physically implemented. Any

read/write operation to locations [00H] and [02H] ac-

cesses the Data Memory locations pointed to by MP0

and MP1 respectively. Reading location 00H or 02H in-

directly will return a result of 00H. Writing indirectly will

lead to no operation.

The function of data movement between two indirect ad-

dressing registers is not supported. The memory pointer

registers, MP0 and MP1, are both 8-bit registers used to

access the Data Memory by combining corresponding

indirect addressing registers. MP0 can only be applied

to the data memory, while MP1 can be applied to both

the data memory and the LCD display memory.

Accumulator - ACC

The accumulator, ACC, is related to the ALU operations.

It is also mapped to location 05H in the Data Memory

and is capable of operating with immediate data. The

data movement between two data memory locations

must pass through the ACC.

Status Register - STATUS

The status register is 8 bits wide and contains, a carry

flag (C), an auxiliary carry flag (AC), a zero flag (Z), an

overflow flag (OV), a power down flag (PDF), and a

watchdog time-out flag (TO). It also records the status

information and controls the operation sequence.

Except for the TO and PDF flags, bits in the status reg-

ister can be altered by instructions similar to other reg-

isters. Data written into the status register does not alter

the TO or PDF flags. Operations related to the status

register, however, may yield different results from those

intended. The TO and PDF flags can only be changed

by a Watchdog Timer overflow, a device power-up, or

clearing the Watchdog Timer and executing the ²HALT²

instruction. The Z, OV, AC, and C flags reflect the status

of the latest operations.

On entering the interrupt sequence or executing a sub-

routine call, the status register will not be automatically

pushed onto the stack. If the contents of the status is im-

portant, and if the subroutine is likely to corrupt the sta-

tus register, the precautions should be taken to save it

properly.

Arithmetic and Logic Unit - ALU

This circuit performs 8-bit arithmetic and logic opera-

tions and provides the following functions:

· Arithmetic operations - ADD, ADC, SUB, SBC, DAA

· Logic operations - AND, OR, XOR, CPL

· Rotation - RL, RR, RLC, RRC

· Increment and Decrement - INC, DEC

· Branch decision - SZ, SNZ, SIZ, SDZ etc.

The ALU not only saves the results of a data operation

but also changes the status register.

Interrupts

The device provides two external interrupts, two internal

timer/event counter interrupts, an internal time base in-

terrupt and an internal real time clock interrupt. The in-

terrupt control register 0, INTC0, and the interrupt

control register 1, INTC1, both contain the interrupt con-

trol bits that are used to set the enable/disable status

and interrupt request flags.

Once an interrupt subroutine is serviced, other inter-

rupts are all blocked as the EMI bit is automatically

cleared, which may prevent any further interrupt nest-

ing. Other interrupt requests may take place during this

interval, but only the interrupt request flag will be re-

corded. If a certain interrupt requires servicing within the

Bit No.

0

1

2

3

4

5

6, 7

Label

C

AC

Z

OV

PDF

TO

¾

Function

C is set if an operation results in a carry during an addition operation or if a borrow does not

take place during a subtraction operation; otherwise C is cleared. C is also affected by a ro-

tate through carry instruction.

AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from

the high nibble into the low nibble in subtraction; otherwise AC is cleared.

Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.

OV is set if an operation results in a carry into the highest-order bit but not a carry out of the

highest-order bit, or vice versa; otherwise OV is cleared.

PDF is cleared by either a system power-up or executing the ²CLR WDT² instruction. PDF is

set by executing the ²HALT² instruction.

TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO

is set by a WDT time-out.

Unused bit, read as ²0²

Status (0AH) Register

Rev. 1.00

11

December 19, 2006

Share Link: