HX6408 Ver la hoja de datos (PDF) - Honeywell International
Número de pieza
componentes Descripción
Lista de partido
HX6408 Datasheet PDF : 11 Pages
| |||
HX6408
Advanced Information
FUNCTIONAL DIAGRAM
36 LEAD FLAT PACK PINOUT
An
NWE
NSL
NCS
NOE
Memory
Array
WE • CS
NWE • CS
DQ(0:7)
All controls must be enabled
for signal to pass.
# = number of buffers,
Default = 1
1 = enabled
Signal #
Signal
HX6408
A0 1 Top View 36 (NSL)
A1 2
35 A18
A2 3
34 A17
A3 4
33 A16
A4 5
32 A15
NCS 6
31 NOE
D0 7
30 D4
D1 8
29 D5
VDD 9
28 VSS
VSS 10
27 VDD
D2 11
26 D6
D3 12
25 D7
NWE 13
24 A14
A5 14
23 A13
A6 15
22 A12
A7 16
21 A11
A8 17
20 A10
A9 18
19 NAS
SIGNAL DEFINITIONS
A: 0-18 Address input pins, which select a particular eight-bit word within the memory array.
DQ: 0-7 Bidirectional data pins, which serve as data outputs during a read operation and as data inputs
during a write operation.
NCS
Negative chip select, when at a low level allows normal read or write operation. When at a high level
NCS forces the SRAM to a precharge condition, holds the data output drivers in a high impedance
state. If this signal is not used it must be connected to VSS.
NWE
Negative write enable, when at a low level activates a write operation and holds the data output
drivers in a high impedance state. When at a high level NWE allows normal read operation.
NOE
Negative output enable, when at a high level holds the data output drivers in a high impedance
state. When at a low level, the data output driver state is defined by NCS, NWE and NSL. This
signal is asynchronous.
NSL
Not sleep, when at a high level allows normal operation. When at a low level NSL forces the SRAM
to a precharge condition, holds the data output drivers in a high impedance state and disables all the
input buffers except the NCS and NOE input buffers. If this signal is not used it must be connected
to VDD. This signal is asynchronous. The HX6408 may be ordered without the sleep mode option
and pin 36 is then a NC.
2 www.honeywell.com
Share Link: 