85301AG Ver la hoja de datos (PDF) - Integrated Circuit Systems
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85301AG Datasheet PDF : 19 Pages
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Integrated
Circuit
Systems, Inc.
ICS85301
2:1
DIFFERENTIAL-TO-LVPECL MULTIPLEXER
TABLE 4E. LVPECL DC CHARACTERISTICS, VCC = 2.5V ± 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
IIH
Input High
Current
PCLK0, nPCLK0,
PCLK1, nPCLK1
VCC = VIN = 2.625V
IIL
PCLK0, PCLK1
Input Low Current
nPCLK0, nPCLK1
VCC = 2.625V, VIN = 0V
V = 2.625V, V = 0V
-10
-150
CC
IN
VPP
Peak-to-Peak Input Voltage
150
VCMR
Common Mode Input Voltage; NOTE 1, 2
1.2
VOH
Output High Voltage; NOTE 3
1.25
VOL
Output Low Voltage; NOTE 3
0.48
VBB
Bias Voltage
0.935
NOTE 1: Common mode voltage is defined as V .
IH
NOTE 2: For single ended applications, the maximum input voltage for PCLKx, nPCLKx is VCC + 0.3V.
NOTE 3: Outputs terminated with 50Ω to VCC - 2V. .
Maximum
150
1200
2.5
1.705
1.005
1.305
Units
µA
µA
µA
mV
V
V
V
V
TABLE
5A.
AC
CHARACTERISTICS,
V
CC
=
3.3V±5%,
TA
=
-40°C
TO
85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
fMAX
tPD
tsk(pp)
Output Frequency
Propagation Delay; NOTE 1
Part-to-Part Skew; NOTE 2, 3
3
240
490
150
tsk(i)
Input Skew
25
tjit
Buffer Additive Phase Jitter, RMS; 622MHz (Integration Range:
refer to Additive Phase Jitter section
12KHz - 20MHz)
0.009
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
100
200
48
52
MUX_ISOL MUX Isolation
f = 622MHz
-55
All parameters measured at f ≤ 1.7GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Units
GHz
ps
ps
ps
ps
ps
%
dBm
TABLE 5B. AC CHARACTERISTICS, VCC = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
fMAX
tPD
tsk(pp)
Output Frequency
Propagation Delay; NOTE 1
Part-to-Part Skew; NOTE 2, 3
tsk(i)
tjit
tR / tF
odc
Input Skew
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
Output Rise/Fall Time
Output Duty Cycle
622MHz (Integration Range:
12KHz - 20MHz)
20% to 80%
MUX_ MUX Isolation
ISOL
For notes, see Table 5A above.
f = 622MHz
Minimum
240
100
47
Typical
0.009
-55
Maximum
3
490
150
25
200
53
Units
GHz
ps
ps
ps
ps
ps
%
dBm
85301AK
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2006
4
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