ICS9248YF-138 Ver la hoja de datos (PDF) - Integrated Circuit Systems
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ICS9248YF-138
Integrated Circuit Systems
ICS9248YF-138 Datasheet PDF : 12 Pages
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ICS9248-138
Preliminary Product Preview
Byte 1: SDRAM Control Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
31
32
33
35
36
37
PWD
DESCRIPTION
X FS2#
X FS1#
1 SDRAM_F
1 SDRAM7
1 SDRAM6
1 SDRAM5
1 SDRAM4
1 SDRAM3
Byte 3: 3V66, Control Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
7
8
9
PWD
DESCRIPTION
X FS4#
1 Reserved
1 Reserved
X FS3#
1 Reserved
1 3V66-0
1 3V66-1
1 3V66-2
Byte 2: PCI, Control Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit 7 -
1 FS0#
Bit 6 20
1 PCICLK6
Bit 5 19 1 PCICLK5
Bit 4 17 1 PCICLK4
Bit 3 16
1 PCICLK3
Bit 2 15 1 PCICLK2
Bit 1 13 1 PCICLK1
Bit 0 12
1 PCICLK0
Byte 4: Control Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit 7 -
1 Reserved
Bit 6 -
1 Reserved
Bit 5 -
1 Reserved
Bit 4 -
1 Reserved
Bit 3 -
1 Reserved
Bit 2 26
1 48MHz-0
Bit 1 27
1 48MHz-1
Bit 0 28
1 24_48MHz
Byte 5: Control Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit7 -
X SEL24_48#
Bit6 1
1 REF0
Bit5 47 1 IOAPIC
Bit4 44 1 CPUCLK1
Bit3 45 1 CPUCLK0
Bit2 39 1 SDRAM2
Bit1 40 1 SDRAM1
Bit0 41 1 SDRAM0
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inferted logic
load of the input frequency select pin conditions.
Byte 6: Control Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit7 -
0 Reserved (Note)
Bit6 -
0 Reserved (Note)
Bit5 -
0 Reserved (Note)
Bit4 -
0 Reserved (Note)
Bit3 -
0 Reserved (Note)
Bit2 -
1 Reserved (Note)
Bit1 -
1 Reserved (Note)
Bit0 -
0 Reserved (Note)
Note: Dont write into this register, writing into this
register can cause malfunction
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