ICS9248-195 Ver la hoja de datos (PDF) - Integrated Circuit Systems
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ICS9248-195
Integrated Circuit Systems
ICS9248-195 Datasheet PDF : 16 Pages
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ICS9248 - 195
Byte 1: Active/Inactive Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
46
-
-
39
42
43
45
PWD
1
1
0
0
1
1
1
1
Description
(Reserved)
CPUCLK_F (En/Dis)
(Reserved)
(Reserved)
SDRAM_F (En/Dis)
CPUCLK2 (En/Dis)
CPUCLK1 (En/Dis)
CPUCLK0 (En/Dis)
Byte 2: Active/Inactive Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
7
18
17
13
12
11
10
8
PWD
1
1
1
1
1
1
1
1
Description
PCICLK_F (En/Dis)
PCICLK6 (En/Dis)
PCICLK5 (En/Dis)
PCICLK4 (En/Dis)
PCICLK3 (En/Dis)
PCICLK2 (En/Dis)
PCICLK1 (En/Dis)
PCICLK0 (En/Dis)
Byte 3: Active/Inactive Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
-
28
29
31
32
PWD
1
0
0
0
1
1
1
1
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
SDRAM7 (En/Dis)
SDRAM6 (En/Dis)
SDRAM5 (En/Dis)
SDRAM4 (En/Dis)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
2. Latched register values will be inverted from pin values. Default latch condition is for all latched inputs to
be floating (pulled up via internal resistor) at power-up.
0375D—02/02/04
4
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