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ICS9248-99

Frequency Generator & Integrated Buffers for Celeron & PII/III™

Integrated Circuit Systems 

ICS9248-99

Preliminary Product Preview

Absolute Maximum Ratings

Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 4.6 V

I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V

Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are

stress specifications only and functional operation of the device at these or any other conditions above those listed in the

operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods

may affect product reliability.

Group Timing Relationship Table

Group

CPU 66MHz

CPU 100MHz

CPU 133MHz

Offset Tolerance Offset Tolerance Offset Tolerance

CPU to SDRAM 2.5ns

500ps

5.0ns

500ps

0.0ns

500ps

CPU to 3V66

7.5ns

500ps

5.0ns

500ps

0.0ns

500ps

SDRAM to 3V66 0.0ns

500ps

0.0ns

500ps

0.0ns

500ps

3V66 to PCI 1.5-3.5ns 500ps 1.5-3.5ns 500ps 1.5-3.5ns 500ps

PCI to PCI

0.0ns

1.0ns

0.0ns

1.0ns

0.0ns

1.0ns

USB & DOT Asynch N/A Asynch N/A Asynch N/A

Electrical Characteristics - Input/Supply/Common Output Parameters

TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

Input High Voltage

VIH

Input Low Voltage

VIL

Input High Current

IIH

VIN = VDD

Input Low Current

IIL1

VIN = 0 V; Inputs with no pull-up resistors

Input Low Current

IIL2

VIN = 0 V; Inputs with pull-up resistors

Operating

IDD3.3OP CL = 0 pF; Select @ 66M

Supply Current

Power Down

Supply Current

IDD3.3PD CL = 0 pF; With input address to Vdd or GND

Input frequency

Fi

VDD = 3.3 V;

Pin Inductance

Lpin

Input Capacitance1

CIN Logic Inputs

Cout Out put pin capacitance

Transition Time1

Settling Time1

Clk Stabilization1

CINX

Ttrans

Ts

TSTAB

X1 & X2 pins

To 1st crossing of target Freq.

From 1st crossing to 1% target Freq.

From VDD = 3.3 V to 1% target Freq.

Delay

tPZH,tPZH output enable delay (all outputs)

tPLZ,tPZH output disable delay (all outputs)

1Guarenteed by design, not 100% tested in production.

2

VSS-0.3

-5

VDD+0.3 V

0.8

V

5

µA

-5 2.0

µA

-200 -100

µA

60 100 mA

400 600

14.318

7

5

6

27

45

3

3

3

1

10

1

10

µA

MHz

nH

pF

pF

pF

mS

mS

mS

nS

nS

Third party brands and names are the property of their respective owners.

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