ICS9250-14 Ver la hoja de datos (PDF) - Integrated Circuit Systems

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ICS9250-14

Frequency Timing Generator for Pentium II Systems

Integrated Circuit Systems 

ICS9250 - 14

Preliminary Product Preview

Power Down Waveform

Note

1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all

the output clocks are driven Low on their next High to Low tranistiion.

2. Power-up latency <3ms.

3. Waveform shown for 100MHz

4

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