ICS9250-26 Ver la hoja de datos (PDF) - Integrated Circuit Systems

Número de pieza

componentes Descripción

Lista de partido

ICS9250-26

Frequency Generator & Integrated Buffers for Celeron & PII/III™

Integrated Circuit Systems 

ICS9250-26

Maximum Allowed Current

810E

Condition

Powerdown Mode

(PWRDWN# = 0

Full Active 66MHz

SEL1, 0 = 10

Full Active 100MHz

SEL1, 0 = 11

Max 2.5V supply consumption Max 2.5V supply consumption

Max discrete cap loads,

Max discrete cap loads,

Vddq2 = 2.625V

Vddq2 = 3.465V

All static inputs = Vddq3 or GND All static inputs = Vddq3 or GND

10mA

10mA

70mA

280mA

100mA

280mA

Clock Enable Configuration

PD# CPUCLK SDRAM IOAPIC

66MHz

PCICLK

REF,

48MHz

Osc

VCOs

0

LOW

LOW LOW LOW LOW LOW OFF OFF

1

ON

ON

ON

ON

ON

ON ON ON

Power Groups*

VDD0, GND0 = REF & Crystal

VDD1, GND1 = 3V66

VDD2, GND2 = PCICLK

VDD3, GND3 = PLL core

VDD4, GND4 = 48MHz

VDD5, GND5 = SDRAM_F, SDRAM

VDDL0, GNDL0 = CPUCLK

VDDL1, GNDL1 = IOAPIC

* To ensure the processor will power up to the desired frequency, the 3.3V supply to the ICS9250-26 needs to reach a stable

condition before the 2.5V supply does. In most systems, the power up ramp of the 2.5V is slower than the 3.3V ramp. For those

instances, no special requirements are necessary.

3

Share Link: