ICS93716 Ver la hoja de datos (PDF) - Integrated Circuit Systems
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ICS93716 Datasheet PDF : 12 Pages
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ICS9371 6
Timing Requirements
TA = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V, RL = 120Ω, CL=15pF (unless otherwise
PARAMETER
SYMBOL
CONDITIONS
MIN MAX UNITS
Max clock frequency3
freqop
33
233 MHz
Application Frequency
Range3
freqApp
60
170 MHz
Input clock duty cycle
dtin
40
60
%
CLK stabilization
TSTAB
100
µs
Switching Characteristics
TA = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V, RL = 120Ω, CL=15pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITION
MIN TYP MAX UNITS
Low-to high level
propagation delay time
tPLH1
CLK_IN to any output
5.5
ns
High-to low level propagation
delay time
tPHL1
CLK_IN to any output
5.5
ns
Duty Cycle
DC
49
51
%
Input clock slew rate
Cycle to Cycle Jitter1
Phase error
tsl(I)
1
4
v/ns
tcyc-tcyc
66/100/125/133/167MHz
75
ps
t(phase
4
error)
-150
0
50
ps
Output to Output Skew
tskew
75
100
ps
Rise Time, Fall Time
tr, tf
See figure 8
650
950 ps
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies. This is due to the formula: duty cycle=twH/tc, were
the cycle (tc) decreases as the frequency goes up.
3. Switching characteristics guaranteed for application frequency range.
4. Static phase offset shifted by design.
0420E—04/01/03
6
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