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ICSSSTUA32S869B

14-Bit Configurable Registered Buffer for DDR2

Integrated Circuit Systems 

ICSSSTUA32S869B

Advance Information

Output slew rate measurement information (VDD = 1.8 V ± 0.1 V)

All input pulses are supplied by generators having the following characteristics: PRR 10 MHz;

Zo = 50 ; input slew rate = 1 V/ns ± 20%, unless otherwise specified.

VDD

DUT

RL = 50Ω

OUT

TEST POINT

CL = 10 pF

SEE NOTE (1)

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(1) CL includes probe and jig capacitance.

Figure 12 — Load circuit, HIGH-to-LOW slew measurement

OUTPUT

VOH

80%

dv_f

20%

VOL

dt_f

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Figure 13 — Voltage waveforms, HIGH-to-LOW slew rate measurement

DUT

OUT

CL = 10 pF

SEE NOTE (1)

TEST POINT

RL = 50Ω

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(1) CL includes probe and jig capacitance.

Figure 14 — Load circuit, LOW-to-HIGH slew measurement

1173—10/28/05

dv_r

OUTPUT

dt_r

80%

20%

VOH

VOL

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Figure 15 — Voltage waveforms, LOW-to-HIGH slew rate measurement

14

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