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ICSSSTUAH32868A

28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

Integrated Device Technology 

ICSSSTUAH32868A

28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

COMMERCIAL TEMPERATURE GRADE

Features

• 28-bit 1:2 registered buffer with parity check functionality

• Supports SSTL_18 JEDEC specification on data inputs

and outputs

• Supports LVCMOS switching levels on CSGEN and

RESET inputs

• Low voltage operation: VDD = 1.7V to 1.9V

• Available in 176-ball LFBGA package

Applications

• DDR2 Memory Modules

• Provides complete DDR DIMM solution with

ICS98ULPA877A or IDTCSPUA877A

• Ideal for DDR2 400, 533, and 667

Block Diagram

M2

RESET

CLK L1

CLK M1

VREF A5, AB5

DCKE0, D1, C1

DCKE1

2

DODT0, N1, P1

DODT1

2

DCS0

K1

2

D

F2, E2 QCKE0A,

QCKE1A

2

CK Q

R

H8, F8 QCKE0B,

QCKE1B

2

D

N2, P2 QODT0A,

QODT1A

2

CK Q

R

M7, M8 QODT0B,

QODT1B

D

CK Q

R

K2 QCS0A

L7 QCS0B

CSGEN L2

DCS1

J1

D

CK Q

R

J2 QCS1A

L8 QCS1B

D1 A2

One of 22 Channels

D CE

CK Q

R

A7

Q1A

A8

Q1B

TO 21 OTHER CHANNELS

(D2-D5, D7, D9-D12, D17-D28)

28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

2

ICSSSTUAH32868A

7115/9

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