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IDT54FCT16270TPVB

FAST CMOS 18-BIT R/W BUFFER

Integrated Device Technology 

IDT54/74FCT162701T/AT

FAST CMOS 18-BIT R/W BUFFER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTIONAL DESCRIPTION:

This device is useful as a read/write buffer for modular high

end designs. It provides multi-level buffering in the write path

and single deep buffering in the read path, and is suited to

write back cache implementation. The read path provides a

transparent latch.

The four deep FIFO uses one clock with two clock enable

pins, WCE and RCE to clock data in and out. The FIFO has

an external full flag which goes LOW when the FIFO is full.

Internal read and write pointers keep track of the words stored

in the FIFO. A write attempt to a full FIFO is ignored. An

attempt to read from an empty FIFO will have no effect and the

last read data remains at the output of the FIFO. The FIFO

may be reset by the synchronous RESET input. This resets

the read and write pointers to the original "empty" condition

and also sets all B outputs = 1. Simultaneous read and write

attempts (clock data into FIFO as well as clock data out of

FIFO) are possible except on FIFO empty and full boundaries.

When the FIFO is empty, and a simultaneous read and write

is attempted, the read is ignored while the write is executed.

If the same is attempted when the FIFO is full, the write is

ignored while the read is executed. Normal operation of the

four deep FIFO in the write path is independent of the read

path operation.

Power, ground and data pin positions on the FCT162701T

match those on the FCT16501T/162501T, allowing an easy

upgrade.

APPLICATIONS: 486 INTERFACE

CacheRAM

Coprocessor

i486

W/R

CLK

FCT162701T

A

B

CLK,WCE,

RCE, RST

LE,OEBA,

OEAB

PAL

Figure 1. FCT162701T Application Example

DRAM

2915 drw 04

5.15

4

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