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IDT7008S25GJ

HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT7008S/L

High-Speed 64K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)

tWC

ADDRESS

tHZ (7)

OE

tAW

CE or SEM(9,10)

R/W

DATAOUT

DATAIN

tAS(6)

(4)

tWP (2)

tWZ (7)

tDW

tWR (3)

tOW

tDH

(4)

3198 drw 09

Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)

tWC

ADDRESS

CE or SEM(9,10)

R/W

DATAIN

tAS (6)

tAW

tEW (2)

tWR(3)

tDW

tDH

3198 drw 10

NOTES:

1. R/W or CE must be HIGH during all address transitions.

2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.

3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, CE or R/W.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure

2).

8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be

placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as

the specified tWP.

9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.

10. Refer to Chip Enable Truth Table.

10

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