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IDT7024L(2018) Ver la hoja de datos (PDF) - Integrated Device Technology

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componentes Descripción
Lista de partido
IDT7024L
(Rev.:2018)
IDT
Integrated Device Technology IDT
IDT7024L Datasheet PDF : 22 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
Capacitance (TA = +25°C, f = 1.0MHz)(1)
Symbol
Parameter
Conditions(2) Max. Unit
CIN Input Capacitance
VIN = 3dV
9 pF
COUT Output Capacitance
VOUT = 3dV
10 pF
NOTES:
2740 tbl 07
1. This parameter are determined by device characterization, but is not
production tested.
2. 3dV references the interpolated capacitance when the input and
output signals switch from 0V to 3V or from 3V to 0V.
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
7024S
Symbol
|ILI|
Parameter
Input Leakage Current(1)
Test Conditions
VCC = 5.5V, VIN = 0V to VCC
Min.
Max.
___
10
|ILO|
Output Leakage Current
VOL
Output Low Voltage
CE = VIH, VOUT = 0V to VCC
IOL = +4mA
___
10
___
0.4
VOH
Output High Voltage
IOH = -4mA
2.4
___
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
7024L
Min.
Max.
___
5
___
5
___
0.4
2.4
___
Unit
µA
µA
V
V
2740 tbl 08
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VCC = 5.0V ± 10%)
7024X15
Com'l Only
7024X17
Com'l Only
7024X20
Com'l, Ind
& Military
7024X25
Com'l &
Military
Symbol
Parameter
Test Condition
Version
Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
CE = VIL,
Outputs Disabled
SEM = VIH
f = fMAX(3)
COM'L
MIL &
IND
S 170
310
170
310
160
290
155
265 mA
L
170
260
170
260
160
240
155
220
S
____
____
____
____
160 370 155 340
L
____
____
____
____
160 320 155 280
ISB1
Standby Current
(Both Ports - TTL
Level Inputs)
CER = CEL = VIH
SEMR = SEML = VIH
f = fMAX(3)
COM'L
S
20
60
20
60
20
60
16
60 mA
L
20
50
20
50
20
50
16
50
MIL &
S
____
____
____
____
20
90
16
80
IND
L
____
____
____
____
20
70
16
65
ISB2
Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and CE"B" = VIH(5)
Active Port Outputs Disabled,
f=fMAX(3)
SEMR = SEML = VIH
COM'L
S 105 190 105 190
95
180
90
170 mA
L 105 160 105 160
95
150
90
140
MIL &
IND
S
____
____
____
____
95
240
90
215
L
____
____
____
____
95
210
90
180
ISB3
Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CEL and
CER > VCC - 0.2V,
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
SEMR = SEML > VCC - 0.2V
COM'L
S 1.0
15
1.0
15
1.0
15
1.0
15 mA
L 0.2
5
0.2
5
0.2
5
0.2
5
MIL &
IND
S
____
____
____
____
1.0
30
1.0
30
L
____
____
____
____
0.2
10
0.2
10
ISB4
Full Standby Current
(One Port -
CMOS Level Inputs)
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
SEMR = SEML > VCC - 0.2V
VIN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Disabled,
f = fMAX(3)
COM'L
S 100 170 100 170
90
155
85
145 mA
L 100 140 100 140
90
130
85
120
MIL &
IND
S
____
____
____
____
90
225
85
200
L
____
____
____
____
90
200
85
170
NOTES:
2740 tbl 09a
1. 'X' in part number indicates power rating (S or L)
2. VCC = 5V, TA = +25°C, and are not production tested. ICC DC = 120mA (TYP.)
3. At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6.542

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