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IDT71321

HIGH-SPEED 2K x 16 CMOS DUAL-PORT STATIC RAMS

Integrated Device Technology 

IDT71321SA/LA AND IDT71421SA/LA

HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(2)

Symbol

Parameter

71321X20 71321X25 71321X35 71321X55 71321X100

71421X25 71421X35 71421X55 71421X100

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

Read Cycle

tRC

tAA

tACE

tAOE

tOH

tLZ

tHZ

tPU

tPD

Read Cycle Time

Address Access Time

Chip Enable Access Time

Output Enable Access Time

Output Hold From Address Change

Output Low-Z Time(1,3)

Output High-Z Time(1,3)

Chip Enable to Power Up Time(3)

Chip Disable to Power Down Time(3)

20 —

— 20

— 20

11

3—

0—

— 10

0—

— 20

25 — 35

— 25 —

— 25 —

— 12 —

3—3

0—0

— 10 —

0—0

— 25 —

NOTES:

1. Transition is measured ±500mV from Low or High-impedance voltage Output Test Load (Figure 2).

2. “X” in part numbers indicates power rating (SA or LA).

3. This parameter is guaranteed by device characterization, but is not production tested.

— 55

35 —

35 —

20 —

—3

—5

15 —

—0

35 —

— 100 — ns

55 — 100 ns

55 — 100 ns

25 — 40 ns

— 10 — ns

— 5 — ns

25 — 40 ns

— 0 — ns

50 — 50 ns

2689 tbl 09

TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE (1)

tRC

ADDRESS

tAA

tOH

tOH

DATAOUT

BUSYOUT

PREVIOUS DATA VALID

DATA VALID

tBDDH (2,3)

2691 drw 06

NOTES:

1. R/W = VIH, CE = VIL, and OE = VIL. Address is valid prior to or coincidental with CE transition Low.

2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read

operations BUSY has no relationship to valid output data.

3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.

6.03

5

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