IDT72205LB(2000) Ver la hoja de datos (PDF) - Integrated Device Technology

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IDT72205LB
(Rev.:2000)

CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18

Integrated Device Technology 

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™

256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18

WCLK

D0 - D17

t CLKH

t CLK

t CLKL

t DS

DATA IN VALID

tENS

tWFF

RCLK

t SKEW1(1)

Commercial And Industrial Temperature Ranges

t DH

tENH

t WFF

NO OPERATION

2766 drw 07

NOTES:

1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the

time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.

Figure 5. Write Cycle Timing

RCLK

t ENS

Q0 - Q17

WCLK

t CLKH

t CLK

t CLKL

tENH

tREF

NO OPERATION

t OLZ

tA

t OE

t

(1)

SKEW2

t REF

VALID DATA

t OHZ

2766 drw 08

NOTE:

1. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. If the

time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK edge.

Figure 6. Read Cycle Timing

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