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IDT723644

CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

Integrated Device Technology 

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

CLKB

FFB/IRB HIGH

CSB

W/RB

MBB

ENB

B0-B17

tENS1

tENS1

tENS2

tENS2

tDS

tENH

tENH

tDH

tENS2

tENS2

DATA SIZE TABLE .OR WORD WRITES TO .I.O2

SIZE MODE(1)

WRITE NO. DATA WRITTEN TO FIFO2

BM

SIZE

BE

B17-B9

B8-B0

A35-A27

tENH

tENH

tENH

3270 drw11

DATA READ FROM FIFO2

A26-A18

A17-A9

A8-A0

H

L

H

1

A

B

A

B

C

D

2

C

D

H

L

L

1

C

D

A

B

C

D

2

A

B

NOTE:

1. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.

Figure 9. Port B Word Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)

CLKB

FFB/IRB HIGH

tENS1

tENH

CSB

W/RB

MBB

ENB

B0-B8

tENS1

tENS2

tENS2

tDS

tENH

tENH

tDH

tENS2

tENH

tENH

3270 drw12

DATA SIZE TABLE .OR BYTE WRITES TO .I.O2

SIZE MODE(1)

WRITE DATA WRITTEN

NO.

TO FIFO2

DATA READ FROM FIFO2

BM

SIZE

BE

B8-B0

A35-A27

A26-A18

A17-A9

A8-A0

1

A

2

B

H

H

H

3

C

A

B

C

D

4

D

1

D

2

C

H

H

L

3

B

A

B

C

D

4

A

NOTE:

1. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.

Figure 10. Port B Byte Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)

20

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