IDT723631(2002) Ver la hoja de datos (PDF) - Integrated Device Technology
Número de pieza
componentes Descripción
fabricante
IDT723631 Datasheet PDF : 21 Pages
| |||
IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF
SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5.0V ± 10%, TA = -40°C to +85°C)
Symbol
Parameter
Commercial
IDT723631L15
IDT723641L15
IDT723651L15
Min.
Max.
Com’l & Ind’l(1)
IDT723631L20
IDT723641L20
IDT723651L20
Min.
Max.
Unit
fS
Clock Frequency, CLKA or CLKB
–
66.7
–
50
MHz
tCLK
Clock Cycle Time, CLKA or CLKB
15
–
20
–
ns
tCLKH Pulse Duration, CLKA or CLKB HIGH
6
–
8
–
ns
tCLKL
Pulse Duration, CLKA or CLKB LOW
6
–
8
–
ns
tDS
Setup Time, A0-A35 before CLKA↑and B0-B35 before CLKB↑
5
–
6
–
ns
tENS1
Setup Time, ENA to CLKA↑; ENB to CLKB↑
5
–
6
–
ns
tENS2
Setup Time, CSA, W/RA, and MBA to CLKA↑; CSB, W/RB and MBB to CLKB↑
7
–
7.5
–
ns
tRMS
Setup Time, RTM and RFM to CLKB↑
tRSTS
Setup Time, RST LOW before CLKA↑ or CLKB↑(2)
tFSS
Setup Time, FS0 and FS1 before RST HIGH
6
–
6.5
–
ns
5
–
6
–
ns
9
–
10
–
ns
tSDS(3)
tSENS(3)
Setup Time, FS0/SD before CLKA↑
Setup Time, FS1/SEN before CLKA↑
5
–
6
–
ns
5
–
6
–
ns
tDH
Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑
0
–
0
–
ns
tENH1 Hold Time, ENA after CLKA↑; ENB after CLKB↑
0
–
0
–
ns
tENH2
Hold Time, CSA, W/RA, and MBA after CLKA↑; CSB, W/RB and MBB after CLKB↑
0
–
0
–
ns
tRMH
tRSTH
tFSH
tSPH(3)
Hold Time, RTM and RFM after CLKB↑
Hold Time, RST LOW after CLKA↑ or CLKB↑(2)
Hold Time, FS0 and FS1 after RST HIGH
Hold Time, FS1/SEN HIGH after RST HIGH
0
–
0
–
ns
5
–
6
–
ns
0
–
0
–
ns
0
–
0
–
ns
tSDH(3)
tSENH(3)
Hold Time, FS0/SD after CLKA↑
Hold Time, FS1/SEN after CLKA↑
0
–
0
–
ns
0
–
0
–
ns
tSKEW1(4) Skew Time, between CLKA↑ and CLKB↑ for OR and IR
tSKEW2(4) Skew Time, between CLKA↑and CLKB↑ for AE and AF
9
–
11
–
ns
12
–
16
–
ns
NOTES:
1. Industrial temperature range product for 20ns is available as a standard device.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Only applies when serial load method is used to program flag Offset registers.
4. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
5. Design simulated but not tested (typical values).
7
Share Link: 