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IDT723631 Datasheet PDF : 23 Pages
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IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
ready flag is HIGH, a memory location is free in the SRAM to
write new data. No memory locations are free when the input-
ready flag is LOW and attempted writes to the FIFO are
ignored.
Each time a word is written to a FIFO, its write pointer is
incremented. The state machine that controls an input-ready
flag monitors a write-pointer and read pointer comparator that
indicates when the FIFO SRAM status is full, full-1, or full-2.
From the time a word is read from a FIFO, its previous memory
location is ready to be written in a minimum of three cycles of
CLKA. Therefore, an input-ready flag is LOW if less than two
cycles of CLKA have elapsed since the next memory write
location has been read. The second LOW-to-HIGH transition
on CLKA after the read sets the input-ready flag HIGH, and
data can be written in the following cycle.
A LOW-to-HIGH transition on CLKA begins the first syn-
chronization cycle of a read if the clock transition occurs at
time tSKEW1 or greater after the read. Otherwise, the subse-
quent CLKA cycle may be the first synchronization cycle (see
Figure 7).
ALMOST-EMPTY FLAG (AE)
The almost-empty flag of a FIFO is synchronized to the
port clock that reads data from its array (CLKB). The state
machine that controls an almost-empty flag monitors a write-
pointer and read-pointer comparator that indicates when the
FIFO SRAM status is almost empty, almost empty+1, or
almost empty+2. The almost-empty state is defined by the
contents of register X. This register is loaded with a preset
value during a FIFO reset,programmed from port A, or pro-
grammed serially (see almost-empty flag and almost-full flag
offset programming above). The almost-empty flag is LOW
when the FIFO contains X or less words and is HIGH when the
FIFO contains (X+1) or more words. A data word present in
the FIFO output register has been read from memory.
Two LOW-to-HIGH transitions of CLKB are required after
a FIFO write for the almost-empty flag to reflect the new level
of fill; therefore, the almost-empty flag of a FIFO containing
(X+1) or more words remains LOW if two cycles of CLKB have
not elapsed since the write that filled the memory to the (X+1)
level. An almost-empty flag is set HIGH by the second LOW-
to-HIGH transition of CLKB after the FIFO write that fills
memory to the (X+1) level. A LOW-to-HIGH transition of
CLKB begins the first synchronization cycle if it occurs at time
tSKEW2 or greater after the write that fills the FIFO to (X+1)
words. Otherwise, the subsequent CLKB cycle may be the
first synchronization cycle (see Figure 8).
ALMOST-FULL FLAG (AF)
The almost-full flag of a FIFO is synchronized to the port
clock that writes data to its array (CLKA). The state machine
that controls an almost-full flag monitors a write-pointer and
read-pointer comparator that indicates when the FIFO SRAM
status is almost full, almost full-1, or almost full-2. The almost-
full state is defined by the contents of register Y. This register
is loaded with a preset value during a FIFO reset, programmed
from port A, or programmed serially (see almost-empty flag
and almost-full flag offset programming). The almost-full flag
is LOW when the number of words in the FIFO is greater than
or equal to (512-Y), (1024-Y), OR (2048-Y) for the IDT723631,
IDT723641, or IDT723651, respectively. The almost-full flag
is HIGH when the number of words in the FIFO is less than or
equal to [512-(Y+1)], [1024-(Y+1)], or [2048-(Y+1)] for the
IDT723631, IDT723641, or IDT723651, respectively. A data
word present in the FIFO output register has been read from
memory.
Two LOW-to-HIGH transitions of CLKA are required after
a FIFO read for its almost-full flag to reflect the new level of fill.
Therefore, the almost-full flag of a FIFO containing [512/1024/
2048-(Y+1)] or less words remains LOW if two cycles of CLKA
have not elapsed since the read that reduced the number of
words in memory to [512/1024/2048-(Y+1)]. An almost-full
flag is set HIGH by the second LOW-to-HIGH transition of
CLKA after the FIFO read that reduces the number of words
in memory to [512/1024/2048-(Y+1)]. A LOW-to-HIGH tran-
sition of CLKA begins the first synchronization cycle if it occurs
at time tSKEW2 or greater after the read that reduces the
number of words in memory to [512/1024/2048-(Y+1)]. Oth-
erwise, the subsequent CLKA cycle may be the first synchro-
nization cycle (see Figure 9).
Number of Words in the FIFO(1,2)
IDT723631
0
1 to X
(X+1) to [512-(Y+1)]
(512-Y) to 511
512
IDT723641
0
1 to X
(X+1) to [1024-(Y+1)]
(1024-Y) to 1023
1024
IDT723651
0
1 to X
(X+1) to [2048-(Y+1)]
(2048-Y) to 2047
2048
NOTES:
1. X is the almost-empty offset for AE. Y is the almost-full offset for AF.
2. When a word is present in the FIFO output register, its previous memory location is free.
Table 4. FIFO Flag Operation
Synchronized
to CLKB
OR
AE
L
L
H
L
H
H
H
H
H
H
Synchronized
to CLKA
AF
IR
H
H
H
H
H
H
L
H
L
L
3023 tbl 11
11
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