IDT723646(2014) Ver la hoja de datos (PDF) - Integrated Device Technology
Número de pieza
componentes Descripción
fabricante
IDT723646
(Rev.:2014)
(Rev.:2014)
Integrated Device Technology
IDT723646 Datasheet PDF : 35 Pages
| |||
IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLT-
AGE AND OPERATING FREE-AIR TEMPERATURE
(Commercial: VCC = 5.0V ±10%, TA = 0°C to +70°C)
Commercial
IDT723626L15
IDT723636L15
IDT723646L15
Symbol
Parameter
Min.
Max.
Unit
fS
Clock Frequency, CLKA, CLKB, or CLKC
—
66.7
MHz
tCLK
Clock Cycle Time, CLKA, CLKB, or CLKC
15
—
ns
tCLKH
Pulse Duration, CLKA, CLKB, or CLKC HIGH
6
—
ns
tCLKL
Pulse Duration, CLKA, CLKB, OR CLKC LOW
6
—
ns
tDS
Setup Time, A0-A35 before CLKA↑ and C0-C17 before CLKC↑
4
—
ns
tENS1
Setup Time, CSA and W/RA before CLKA↑; CSB before CLKB↑
4.5
—
ns
tENS2
Setup Time, ENA and MBA before CLKA↑; RENB and MBB before CLKB↑ ;
4.5
WENC and MBC before CLKC↑
—
ns
tRSTS
Setup Time, MRS1, MRS2, PRS1, or PRS2 LOW before CLKA↑ or CLKB↑(1)
5
—
ns
tFSS
Setup Time, FS0 and FS1 before MRS1 and MRS2 HIGH
7.5
—
ns
tBES
Setup Time, BE/FWFT before MRS1 and MRS2 HIGH
7.5
—
ns
tSPMS Setup Time, SPM before MRS1 and MRS2 HIGH
7.5
—
ns
tSDS
Setup Time, FS0/SD before CLKA↑
4
—
ns
tSENS
Setup Time, FS1/SEN before CLKA↑
4
—
ns
tFWS
Setup Time, BE/FWFT before CLKA↑
0
—
ns
tDH
Hold Time, A0-A35 after CLKA↑ and C0-C17 after CLKC↑
1
—
ns
tENH
Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, RENB, and MBB
1
after CLKB↑; WENC and MBC after CLKC↑
—
ns
tRSTH
Hold Time, MRS1, MRS2, PRS1 or PRS2 LOW after CLKA↑ or CLKB↑(1)
4
—
ns
tFSH
Hold Time, FS0 and FS1 after MRS1 and MRS2 HIGH
2
—
ns
tBEH
Hold Time, BE/FWFT after MRS1 and MRS2 HIGH
2
—
ns
tSPMH Hold Time, SPM after MRS1 and MRS2 HIGH
2
—
ns
tSDH
Hold Time, FS0/SD after CLKA↑
1
—
ns
tSENH
Hold Time, FS1/SEN HIGH after CLKA↑
1
—
ns
tSPH
Hold Time, FS1/SEN HIGH after MRS1 and MRS2 HIGH
2
—
ns
tSKEW1(2) Skew Time, between CLKA↑and CLKB↑ for EFB/ORB and FFA/IRA; between
7.5
CLKA↑ and CLKC↑ for EFA/ORA and FFC/IRC
—
ns
tSKEW2(2,3) Skew Time, between CLKA↑ and CLKB↑ for AEB and AFA; between CLKA↑ and
12
—
ns
CLKC↑ for AEA and AFC
NOTES:
1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship among CLKA cycle, CLKB cycle, and CLKC cycle.
3. Design simulated, not tested (typical values).
8
Share Link: