72801/72811/72821/72831/72841 DUAL CMOS SyncFIFO™
256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
WCLKA (WCLKB)
tCLKH
tCLK
tCLKL
(DA0 - DA8
DB0 - DB8)
WENA1
(WENB1)
tDS
DATA IN VALID
tENS
tDH
tENH
COMMERCIAL TEMPERATURE
NO OPERATION
WENA2 (WENB2)
(If Applicable)
FFA
(FFB)
RCLKA (RCLKB)
tSKEW1(1)
tWFF
NO OPERATION
tWFF
RENA1, RENA2
(RENB1, RENB2)
3034 drw 07
NOTE:
1. tSKEW1 is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for FFA (FFB) to change during the current clock
cycle. If the time between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW1, then FFA (FFB) may not change
state until the next WCLKA (WCLKB) edge.
Figure 5. Write Cycle Timing
5.15
10