IDT72801L15 Ver la hoja de datos (PDF) - Integrated Device Technology
Número de pieza
componentes Descripción
fabricante
IDT72801L15 Datasheet PDF : 21 Pages
| |||
72801/72811/72821/72831/72841 DUAL CMOS SyncFIFO™
256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
OUTPUTS:
Full Flag (FFA, FFB) — FFA (FFB) will go LOW, inhibiting
further write operations, when Array A (B) is full. If no reads
are performed after reset, FFA (FFB) will go LOW after 256
writes to the 72801's FIFO A (B), 512 writes to the 72811's
FIFO A (B), 1024 writes to the 72821's FIFO A (B), 2048 writes
to the 72831's FIFO A (B), or 4096 writes to the 72841's FIFO
A (B).
FFA (FFB) is synchronized with respect to the LOW-to-
HIGH transition of the write clock WCLKA (WCLKB).
Empty Flag (EFA, EFB) — EFA (EFB) will go LOW,
inhibiting further read operations, when the read pointer is
equal to the write pointer, indicating that Array A (B) is empty.
EFA (EFB) is synchronized with respect to the LOW-to-
HIGH transition of the read clock RCLKA (RCLKB).
Programmable Almost–Full Flag (PAFA, PAFB) — PAFA
(PAFB) will go LOW when the amount of data in Array A (B)
reaches the Almost-Full condition. If no reads are performed
after reset, PAFA (PAFB) will go LOW after (256-m) writes to
the 72801's FIFO A (B), (512-m) writes to the 72811's FIFO A
(B), (1024-m) writes to the 72821's FIFO A (B), (2048-m)
writes to the 72831's FIFO A (B), or (4096-m) writes to the
72841's FIFO A (B).
FFA (FFB) is synchronized with respect to the LOW-to-
HIGH transition of the write clock WCLKA (WCLKB). The
offset “m” is defined in the Full Offset Registers.
If there is no Full offset specified, PAFA (PAFB) will go LOW
at Full-7 words.
PAFA (PAFB) is synchronized with respect to the LOW-to-
HIGH transition of the write clock WCLKA (WCLKB).
Programmable Almost–Empty Flag (PAEA, PAEB) —
PAEA (PAEB) will go LOW when the read pointer is "n+1"
locations less than the write pointer. The offset "n" is defined
in the Empty Offset Registers. If no reads are performed after
reset, PAEA (PAEB) will go HIGH after "n+1" writes to FIFO A
(B).
If there is no Empty offset specified, PAEA (PAEB) will go
LOW at Empty+7 words.
PAEA (PAEB) is synchronized with respect to the LOW-to-
HIGH transition of the read clock RCLKA (RCLKB).
Data Outputs (QA0 – QA8, QB0 – QB8 ) — QA0 - QA8 are
the nine data outputs for memory array A, QB0 - QB8 are the
nine data outputs for memory array B.
TABLE 1: STATUS FLAGS FOR A AND B FIFOS
NUMBER OF WORDS IN ARRAY A
NUMBER OF WORDS IN ARRAY B
72801
72811
72821
0
1 to n(1)
0
1 to n(1)
0
1 to n(1)
(n+1) to (256-(m+1))
(256-m)(2) to 255
(n+1) to (512-(m+1))
(512-m)(2) to 511
(n+1) to (1024-(m+1))
(1024-m)(2) to 1023
256
512
1024
NUMBER OF WORDS IN ARRAY A
NUMBER OF WORDS IN ARRAY B
72831
72841
0
0
1 to n(1)
1 to n(1)
(n+1) to (2048-(m+1))
(n+1) to (4096-(m+1))
(2048-m)(2) to 2047
(4096-m)(2) to 4095
2048
4096
NOTES:
1. n = Empty Offset (n = 7 default value)
2. m = Full Offset (m = 7 default value)
FFA
PAFA PAEA
EFA
FFB
PAFB PAEB
EFB
H
H
L
L
H
H
L
H
H
H
H
H
H
L
H
H
L
L
H
H
FFA
PAFA PAEA
EFA
FFB
PAFB PAEB
EFB
H
H
L
L
H
H
L
H
H
H
H
H
H
L
H
H
L
L
H
H
3034 tbl 09
5.15
8
Share Link: 