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IDT72811

DUAL CMOS SyncFIFO™

Integrated Device Technology 

72801/72811/72821/72831/72841 DUAL CMOS SyncFIFO™

256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9

tRS

RSA (RSB)

COMMERCIAL TEMPERATURE

RENA1, RENA2

(RENB1, RENB2)

WENA1

(WENB1)

WENA2/LDA (1)

(WENB2/LDB)

tRSS

tRSS

tRSS

tRSR

tRSR

tRSR

tRSF

EFA, PAEA

(EFB, PAEB)

tRSF

FFA, PAFA

(FFA, PAFA)

QA0 - QA8

(QB0 - QB8)

tRSF

OEA (OEB) = 1(2)

OEA (OEB) = 0

3034 drw 06

NOTES:

1. Holding WENA2/LDA (WENB2/LDB) HIGH during reset will make the pin act as a second write enable pin. Holding WEN2/LDA (WENB2/LDB) LOW during

reset will make the pin act as a load enable for the programmable flag offset registers.

2. After reset, QA0 - QA8 (QB0 - QB8) will be LOW if OEA (OEB) = 0 and tri-state if OEA (OEB) = 1.

3. The clocks RCLKA, WCLKA (RCLKB, WCLKB) can be free-running during reset.

Figure 4. Reset Timing

5.15

9

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