IDT72805LB(1996) Ver la hoja de datos (PDF) - Integrated Device Technology

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IDT72805LB
(Rev.:1996)

CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1024 x 18

Integrated Device Technology 

IDT72805/72815/72825 CMOS Dual SyncFIFO™

256 x 18, 512 x 18, and 1024 x 18

COMMERCIAL TEMPERATURE RANGE

WIDTH EXPANSION CONFIGURATION — Word width

may be increased simply by connecting together the control

signals of FIFOs A and B. A composite flag should be created

for each of the end-point status flags (EFA and EFB, also FFA

and FFB). The partial status flags (PAEA and PAEB, also

PAFA and PAFB) can be detected from any one device.

Figure 20 demonstrates a 36-bit word width using the two

FIFOs contained in one IDT72805/72815/72825. Any word

width can be attained by adding additional IDT2805/72815/

72825.

18

DATA IN

36 ••

WRITE CLOCK

WRITE ENABLE

FULL FLAG

•

72805/

72815/

72825

RSA DB0 - DB17 RSB

18 DA0 - DA17

FIFO A

RCLKA

FIFO B

WCLKA

WENA

256x18

512x18

1024x18

WCLKB

RENA

WENB

OEA

256x18

512x18

1024x18

EFA

EFB

RCLKB

RENB

OEB

FFA

QB0 - QB17

FFB

QA0-QA17

RESET

EMPTY FLAG

READ CLOCK

READ ENABLE

OUTPUT ENABLE

18 ••

36 DATA OUT

18

3139 drw 20

NOTE:

1. Do not tie any output control signals directly together.

2. Tie FLA, FLB, WXIA, WXIB, RXIA and RXIB to GND.

Figure 20. Block Diagram of the two FIFOs contained in one 72805/72815/72825

configured for a 36-bit Width Expansion

DEPTH EXPANSION CONFIGURATION

(WITH PROGRAMMABLE FLAGS)

The IDT72805LB/72815LB/72825LB can easily be adapted

to applications requiring more than 256/512/1024 words of

buffering. Figure 21 shows a Depth Expansion using the two

FIFOs contained in one IDT72805LB/72815LB/72825LB.

Maximum depth is limited only by signal loading. Follow these

steps:

1. The first FIFO must be designated by grounding the

First Load (FL) control input.

2. All other FIFOs must have FL in the HIGH state.

3. The Write Expansion Out (WXO) pin of each device

must be tied to the Write Expansion In (WXI) pin of

the next FIFO.

4. The Read Expansion Out (RXO) pin of each device

must be tied to the Read Expansion In (RXI) pin of

the next FIFO.

5. All Load (LD) pins are tied together.

6. The Half-Full Flag (HF) is not available in the Depth

Expansion Configuration.

7. EF, FF, PAE, and PAF are created with composite

flags by ORing together every respective flags for

monitoring. The composite PAE and PAF flags are not

precise.

5.17

18

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