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IDT72805LB
Integrated Device Technology
IDT72805LB Datasheet PDF : 26 Pages
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IDT72805LB/72815LB/72825LB/72845LB CMOS Dual SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DEPTH EXPANSION CONFIGURATION (FWFT MODE)
In FWFT mode, the FIFOs can be connected in series (the data outputs
of one FIFO connected to the data inputs of the next) with no external logic
necessary. The resulting configuration provides a total depth equivalent to
the sum of the depths associated with each single FIFO. Figure 31 shows
a depth expansion using one IDT72805LB/72815LB/72825LB/72845LB
devices.
Care should be taken to select FWFT mode during Master Reset for all
FIFOs in the depth expansion configuration. The first word written to an
empty configuration will pass from one FIFO to the next (“ripple down”) until
it finally appears at the outputs of the last FIFO in the chain–no read
operation is necessary but the RCLK of each FIFO must be free-running.
Each time the data word appears at the outputs of one FIFO, that device’s
OR line goes LOW, enabling a write to the next FIFO in line.
For an empty expansion configuration, the amount of time it takes for OR
of the last FIFO in the chain to go LOW (i.e. valid data to appear on the last
FIFO’s outputs) after a word has been written to the first FIFO is the sum of
the delays for each individual FIFO:
(N – 1)*(4*transfer clock) + 3*TRCLK
where N is the number of FIFOs in the expansion and TRCLK is the RCLK
period. Note that extra cycles should be added for the possibility that the
tSKEW1 specification is not met between WCLK and transfer clock, or RCLK
and transfer clock, for the OR flag.
The “ripple down” delay is only noticeable for the first word written to an
empty depth expansion configuration. There will be no delay evident for
subsequent words written to the configuration.
The first free location created by reading from a full depth expansion
configuration will “bubble up” from the last FIFO to the previous one until it
finally moves into the first FIFO of the chain. Each time a free location is
created in one FIFO of the chain, that FIFO’s IR line goes LOW, enabling
the preceding FIFO to write a word to fill it.
For a full expansion configuration, the amount of time it takes for IR of the
first FIFO in the chain to go LOW after a word has been read from the last
FIFO is the sum of the delays for each individual FIFO:
(N – 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. Note that extra cycles should be added for the possibility that the
tSKEW1 specification is not met between RCLK and transfer clock, or WCLK
and transfer clock, for the IR flag.
The Transfer Clock line should be tied to either WCLK or RCLK,
whichever is faster. Both these actions result in data moving, as quickly as
possible, to the end of the chain and free locations to the beginning of the
chain.
HF
PAF
WRITE CLOCK
WRITE ENABLE
INPUT READY
DATA IN n
TRANSFER CLOCK
WCLK
RCLK
W EN
IR
72805
72815
72825
72845
OR
REN
OE
Dn
FL
RXI
Qn
W XI
GND
n
(0,1) GND
VCC
HF
PAE
WCLK
W EN
IR
72805
72815
72825
72845
Dn
FL R XI
(0,1) GND
RCLK
REN
OR
OE
Qn
W XI
VCC
READ CLOCK
READ ENABLE
OUTPUT READY
OUTPUT ENABLE
n
DATA OUT
3139 drw 31
Figure 31. Block Diagram of 512 x 18, 1,024 x 18, 2,048 x 18, 8,192 x 18 Synchronous
FIFO Memory With Programmable Flags used in Depth Expansion Configuration
25
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