IDT72815LB35BG Ver la hoja de datos (PDF) - Integrated Device Technology

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Lista de partido

IDT72815LB35BG

CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1024 x 18

Integrated Device Technology 

IDT72805/72815/72825 CMOS Dual SyncFIFO™

256 x 18, 512 x 18, and 1024 x 18

RCLK

REN

t

ENS

t CLKH

t CLK

t CLKL

tENH

NO OPERATION

EF

Q0 - Q17

OE

WCLK

tREF

tA

t OLZ

t OE

t SKEW2 (1)

COMMERCIAL TEMPERATURE RANGE

t REF

VALID DATA

t OHZ

WEN

3139 drw 06

NOTE:

1. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. If the

time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK edge.

Figure 6. Read Cycle Timing

5.17

10

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