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IDT72801L10

DUAL CMOS SyncFIFO™ DUAL 256 x 9, DUAL 512 x 9, DUAL 1,024 x 9, DUAL 2,048 x 9, DUAL 4,096 x 9, DUAL 8,192 x 9

Integrated Device Technology 

IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM

DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

WCLKA

(WCLKB)

WENA1

(WENB1)

WENA2 (WENB2)

(If Applicable)

tCLKH

tCLKL

tENS

tENS

(4)

tENH

tENH

PAFA

(PAFB)

RCLKA (RCLKB)

tPAF

Full - (m+1) words in FIFO (1)

(2)

Full - m words in FIFO

(3)

tSKEW2

tPAF

RENA1, RENA2

(RENB1, RENB2)

tENS

tENH

3034 drw 11

NOTES:

1. m = PAF offset.

2. (256-m) words for the IDT72801; (512-m) words the IDT72811; (1,024-m) words for the IDT72821; (2,048-m) words for the IDT72831; (4,096-m) words for the IDT72841; or (8,192-m)

words for the IDT72851.

3. tSKEW2 is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for PAFA (PAFB) to change during that clock cycle. If the time between the

rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW2, then PAFA (PAFB) may not change state until the next WCLKA (WCLKB) rising edge.

4. If a write is performed on this rising edge of the write clock, there will be Full - (m-1) words in FIFO A (B) when PAFA (PAFB) goes LOW.

Figure 10. Programmable Full Flag Timing

WCLKA (WCLKB)

WENA1

(WENB1)

WENA2 (WENB2)

(If Applicable)

tCLKH

tCLKL

tENS

tENS

tENH

tENH

PAEA,

PAEB

n words in FIFO (1)

tSKEW2 (2)

tPAE

RCLKA (RCLKB)

RENA1, RENA2

(RENB1, RENB2)

n+1 words in FIFO

tENS

tENH

tPAE

(3)

3034 drw 12

NOTES:

1. n = PAE offset.

2. tSKEW2 is the minimum time between a rising WCLKA (WCLKB) edge and a rising RCLKA (RCLKB) edge for PAEA (PAEB) to change during that clock cycle. If the time between the

rising edge of WCLKA (WCLKB) and the rising edge of RCLKA (RCLKB) is less than tSKEW2, then PAEA (PAEB) may not change state until the next RCLKA (RCLKB) rising edge.

3. If a read is performed on this rising edge of the read clock, there will be Empty + (n-1) words in FIFO A (B) when PAEA (PAEB) goes LOW.

Figure 11. Programmable Empty Flag Timing

12

MARCH 2013

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