IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
WCLKA (WCLKB)
LDA (LDB)
WENA1 (WENB1)
DA0 - DA7
(DB0 - DB7)
tCLK
tCLKL
tENS
tENS
tDS
PAE OFFSET
(LSB)
tENH
tDH
PAE OFFSET
(MSB)
PAF OFFSET
(LSB)
Figure 12. Write Offset Register Timing
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PAF OFFSET
(MSB)
3034 drw 13
RCLKA (RCLKB)
LDA (LDB)
RENA1, RENA2
(RENB1, RENB2)
QA0 - QA7
(QB0 - QB7)
tCLK
tCLKH
tCLKL
tENS
tENS
tENH
tA
DATA IN OUTPUT REGISTER
EMPTY OFFSET
(LSB)
EMPTY OFFSET
(MSB)
FULL OFFSET
(LSB)
FULL OFFSET
(MSB)
3034 drw 14
Figure 13. Read Offset Register Timing
13
MARCH 2013