IDT72V845 Ver la hoja de datos (PDF) - Integrated Device Technology

Número de pieza

componentes Descripción

fabricante

IDT72V845

3.3 VOLT CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18 and DUAL 4,096 x 18

Integrated Device Technology 

IDT72V805/72V815/72V825/72V835/72V845

3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

DEPTH EXPANSION CONFIGURATION — DAISY CHAIN TECHNIQUE

(WITH PROGRAMMABLE FLAGS)

These devices can easily be adapted to applications requiring more than

256/512/1,024/2,048/4,096 words of buffering. Figure 30 shows Depth

Expansion using one IDT72V805/72V815/72V825/72V835/72V845s. Maxi-

mum depth is limited only by signal loading. Follow these steps:

1. The first device must be designated by grounding the First Load (FL)

control input.

2. All other devices must have FL in the HIGH state.

3. The Write Expansion Out (WXO) pin of each device must be tied to the

Write Expansion In (WXI) pin of the next device. See Figure 30.

4. The Read Expansion Out (RXO) pin of each device must be tied to the

Read Expansion In (RXI) pin of the next device. See Figure 30

5. All Load (LD) pins are tied together.

6. The Half-Full flag (HF) is not available in this Depth Expansion

Configuration.

7. EF, FF, PAE, and PAF are created with composite flags by ORing

together every respective flags for monitoring. The composite PAE

and PAF flags are not precise.

8. In Daisy Chain mode, the flag outputs are single register-buffered and

the partial flags are in asynchronous timing mode.

DATA IN

WRITE CLOCK

WRITE ENABLE

RESET

LOAD

FF

PAF

IDT72V845

Vcc

WXOA

WCLKA

WENA

RSA

LDA

RXOA

RCLKA

RENA

OEA

FIFO A

4,096 x 18

DAn

QAn

FLA

FFA/IRA EFA/ORA

PAFA

PAEA

WXIA RXIA

WXOB

WCLKB

WENB

RXOB

RCLKB

RENB

RSB

OEB

DBn

QBn

LDB

FIFO B

4,096 x 18

FFA/IRA EFA/ORA

PAFB

PAEB

WXIB RXIB

FIRST LOAD (FL)

DATA OUT

READ CLOCK

READ ENABLE

OUTPUT ENABLE

EF

PAE

4295 drw 30

Figure 30. Block Diagram of 8,192 x 18 Synchronous FIFO Memory with Programmable Flags

Used in Depth Expansion Configuration

DEPTH EXPANSION CONFIGURATION (FWFT MODE)

In FWFT mode, the FIFOs can be connected in series (the data outputs

of one FIFO connected to the data inputs of the next) with no external logic

necessary. The resulting configuration provides a total depth equivalent to

the sum of the depths associated with each single FIFO. Figure 31 shows

a depth expansion using one IDT72V805/72V815/72V825/72V835/72V845

devices.

Care should be taken to select FWFT mode during Master Reset for all

FIFOs in the depth expansion configuration. The first word written to an

empty configuration will pass from one FIFO to the next (“ripple down”) until

it finally appears at the outputs of the last FIFO in the chain–no read

operation is necessary but the RCLK of each FIFO must be free-running.

Each time the data word appears at the outputs of one FIFO, that device’s

OR line goes LOW, enabling a write to the next FIFO in line.

24

Share Link: