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IDT72V845

3.3 VOLT CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18 and DUAL 4,096 x 18

Integrated Device Technology 

IDT72V805/72V815/72V825/72V835/72V845

3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

TABLE 3 — TRUTH TABLE FOR CONFIGURATION AT RESET

FL RXI WXI

EF/OR

FF/IR

PAE, PAF

FIFO TIMING MODE

0

0

0

0

0

1

0(1)

1

1

0

1

0

1

1

1(2)

1

0 Single Register-Buffered

Empty Flag

1 Triple Register-Buffered

Output Ready Flag

0 Double Register-Buffered

Empty Flag

1 Single Register-Buffered

Empty Flag

0 Single Register-Buffered

Empty Flag

1 Triple Register-Buffered

Output Ready Flag

0 Double Register-Buffered

Empty Flag

1 Single Register-Buffered

Empty Flag

Single Register-Buffered

Full Flag

Double Register-Buffered

Input Ready Flag

Double Register-Buffered

Full Flag

Single Register-Buffered

Full Flag

Single Register-Buffered

Full Flag

Double Register-Buffered

Input Ready Flag

Double Register-Buffered

Full Flag

Single Register-Buffered

Full Flag

Asynchronous

Asynchronous

Asynchronous

Asynchronous

Synchronous

Synchronous

Synchronous

Asynchronous

Standard

FWFT

Standard

Standard

Standard

FWFT

Standard

Standard

NOTES:

1. In a daisy-chain depth expansion, FL is held LOW for the "first load device". The RXI and WXI inputs are driven by the corresponding RXO and WXO outputs of the preceding device.

2. In a daisy-chain depth expansion, FL is held HIGH for members of the expansion other than the "first load device". The RXI and WXI inputs are driven by the corresponding RXO

and WXO outputs of the preceding device.

TABLE 4 — REGISTER-BUFFERED FLAG OUTPUT OPTIONS — IDT STANDARD MODE

Empty Flag (EF)

Buffered Output

Full Flag (FF)

Buffered Output

Partial Flags

Timing Mode

Programming at Reset

FL

RXI

WXI

Flag Timing

Diagrams

Single

Single

Asynch

0

0

0

Figure 9, 10

Single

Single

Sync

1

0

0

Figure 9, 10

Double

Double

Asynch

0

1

0

Figure 24, 26

Double

Double

Synch

1

1

0

Figure 24, 26

TABLE 5 — REGISTER-BUFFERED FLAG OUTPUT OPTIONS — FWFT MODE

Output Ready (OR)

Input Ready (IR)

Partial Flags

Programming at Reset

FL

RXI

WXI

Flag Timing

Diagrams

Triple

Double

Asynch

0

0

1

Figure 27

Triple

Double

Sync

1

0

1

Figure 20, 21

8

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