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IDT72V3622

3.3 VOLT CMOS SyncBiFIFO 256 x 36 x 2 512 x 36 x 2 1/024 x 36 x 2

Integrated Device Technology 

IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

CLKA

CSA LOW

tCLK

tCLKH tCLKL

COMMERCIAL TEMPERATURE RANGE

WRA HIGH

MBA

ENA

tENS2

tENS2

tENH

tENH

IRA HIGH tDS

tDH

A0 - A35

CLKB

W1

(1)

tSKEW1

tCLK

tCLKH tCLKL

1

2

ORB FIFO1Empty

CSB LOW

3

tREF

tREF

W/RB HIGH

MBB LOW

ENB

tENS2

tENH

B0- B35

tA

Old Data in FIFO1 Output Register

W1

4660 drw 10

NOTE:

1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles.

If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB

cycle later than shown.

Figure 8. ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)

17

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