IDT72V3646 Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT72V3646 Datasheet PDF : 36 Pages
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IDIDTT7722VV33662266//7722VV3363663/67/27V23V634664C6MCOMSO3S.33V.3TVriTpRleIPBLuEs BSyUnScFSIyFnOcTMFIFOTM
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PIN DESCRIPTIONS (Continued)
Symbol
Name
I/O
Description
FS1/SEN FlagOffsetSelect1/ I FS1/SEN and FS0/SD are dual-purpose inputs used for flag Offset register programming. During Master Reset,
Serial Enable,
FS1/SEN and FS0/SD, together with SPM, select the flag offset programming method. Three Offset register
programming methods are available: automatically load one of three preset values (8, 16, or 64), parallel
FS0/SD FlagOffsetSelect0/
load from Port A, and serial load.
Serial Data
When serial load is selected for flag Offset register programming, FS1/SEN is used as an enable synchronous to
the LOW-to-HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA load the bit present on
FS0/SD into the X and Y registers. The number of bit writes required to program the Offset registers is 32 for the
72V3626, 36 for the 72V3636, and 40 for the 72V3646. The first bit write stores the Y-register (Y1) MSB and the
last bit write stores the X-register (X2) LSB.
MBA Port A Mailbox
Select
I A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-A35
outputs are active, a HIGH level on MBA selects data from the mail2 register for output and a LOW level selects
FIFO2 output-register data for output.
MBB Port B Mailbox
Select
I A HIGH level on MBB chooses a mailbox register for a Port B read operation. When the B0-B17 outputs are
active, a HIGH level on MBB selects data from the mail1 register for output and a LOW level selects FIFO1 output
register data for output.
MBC Port C Mailbox
Select
I A HIGH level on MBC chooses the mail2 register for a Port C write operation. This pin must be HIGH during
Master Reset.
MBF1
Mail1 Register
Flag
O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the mail1
register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a
Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.
MBF2
Mail2 Register
Flag
O MBF2 is set LOW by a LOW-to-HIGH transition of CLKC that writes data to the mail2 register. Writes to the mail2
register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a
Port A read is selected and MBA is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.
MRS1 Master Reset
I A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the Port B
output register to all zeroes. A LOW-to-HIGH transition on MRS1 selects the programming method (serial or
parallel) and one of three programmable flag default offsets for FIFO1 and FIFO2. It also configures ports B and
C for bus size and endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH
transitions of CLKB must occur while MRS1 is LOW.
MRS2 Master Reset
I A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port A
output register to all zeroes. A LOW-to-HIGH transition on MRS2, toggled simultaneously with MRS1, selects
the programming method (serial or parallel) and one of the three flag default offsets for FIFO2. Four LOW-to-HIGH
transitions of CLKA and four LOW-to-HIGH transitions of CLKC must occur while MRS2 is LOW.
PRS1 PartialReset
I A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets thePort B
output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement,
programming method (serial or parallel), and programmable flag settings are all retained.
PRS2 PartialReset
I A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets thePort A
output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement,
programming method (serial or parallel), and programmable flag settings are all retained.
RENB Port B Read Enable I RENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read data on Port B.
SIZEB Port B
Bus Size Select
I SIZEB determines the bus width of Port B. A HIGH on this pin selects byte (9-bit) bus size. A LOW on this pin
selects word (18-bit) bus size. SIZEB works with SIZEC and BE to select the bus size and endian arrangement
for ports B and C. The level of SIZEB must be static throughout device operation.
SIZEC Port C
Bus Size Select
I SIZEC determines the bus width of Port C. A HIGH on this pin selects byte (9-bit) bus size. A LOW on this pin
selects word (18-bit) bus size. SIZEC works with SIZEB and BE to select the bus size and endian arrangement
for ports B and C. The level of SIZEC must be static throughout device operation.
SPM
Serial Programming I A LOW on this pin selects serial programming of partial flag offsets. A HIGH on this pin selects parallel
Mode
programming or default offsets (8, 16, or 64).
WENC Port C Write Enable I WENC must be HIGH to enable a LOW-to-HIGH transition of CLKC to write data on Port C.
W/RA
Port A Write/
Read Select
I A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH transition of
CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.
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