IDT72V3646 Ver la hoja de datos (PDF) - Integrated Device Technology
Número de pieza
componentes Descripción
fabricante
IDT72V3646 Datasheet PDF : 36 Pages
| |||
IDIDTT7722VV33662266//7722VV3363663/67/27V23V634664C6MCOMSO3S.33V.3TVriTpRleIPBLuEs BSyUnScFSIyFnOcTMFIFOTM
WwIiTthHBBuUsS-M-MatAchTiCngHI2N5G6x2365x62x, 53162x326,x521, 21,x02346x3x62x,21,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT72V3626/72V3636/72V3646 with CLKA,
CLKB and CLKC set to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were
disconnected to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of these device's inputs
driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
PT = VCC x ICC(f) + Σ(CL x VCC2 x fo)
N
where:
N
=
number of used outputs (36-bit (long word), 18-bit (word) or 9-bit (byte) bus size)
CL
=
output capacitance load
fo
=
switching frequency of an output
200
175
150
125
100
75
50
25
0
0
fdata = 1/2 fS
TA = 25οC
CL = 0 pF
VCC = 3.3V
VCC = 3.6V
VCC = 3.0V
10
20
30
40
50
60
70
80
fS Clock Frequency MHz
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)
7
90
100
4665 drw 03
Share Link: 