IDT72V3651 Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT72V3651 Datasheet PDF : 21 Pages
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IDT72V3631/72V3641/72V3651
3.3V CMOS SYNCFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF
SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
IDT72V3631L15
IDT72V3641L15
IDT72V3651L15
IDT72V3631L20
IDT72V3641L20
IDT72V3651L20
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
fS
Clock Frequency, CLKA or CLKB
–
66.7
–
50
MHz
tCLK
Clock Cycle Time, CLKA or CLKB
15
–
20
–
ns
tCLKH
Pulse Duration, CLKA or CLKB HIGH
6
–
8
–
ns
tCLKL
Pulse Duration, CLKA or CLKB LOW
6
–
8
–
ns
tDS
Setup Time, A0-A35 before CLKA↑ and B0-B35
before CLKB↑
5
–
6
–
ns
tENS1
tENS2
Setup Time, ENA to CLKA↑; ENB to CLKB↑
Setup Time, CSA, W/RA, and MBA to CLKA↑;
CSB, W/RB, and MBB to CLKB↑
5
–
6
–
ns
7
–
7.5
–
ns
tRMS
tRSTS
tFSS
Setup Time, RTM and RFM to CLKB↑
Setup Time, RST LOW before CLKA↑
or CLKB↑(1)
Setup Time, FS0 and FS1 before RST HIGH
6
–
6.5
–
ns
5
–
6
–
ns
9
–
10
–
ns
tSDS(2)
tSENS(2)
Setup Time, FS0/SD before CLKA↑
Setup Time, FS1/SEN before CLKA↑
5
–
6
5
–
6
–
ns
–
ns
tDH
Hold Time, A0-A35 after CLKA↑ and B0-B35
after CLKB↑
0.5
–
0.5
–
ns
tENH1
tENH2
Hold Time, ENA after CLKA↑; ENB after CLKB↑
Hold Time, CSA, W/RA, and MBA after CLKA↑;
CSB, W/RB, and MBB after CLKB↑
0.5
–
0.5
0.5
–
0.5
–
ns
–
ns
tRMH
tRSTH
tFSH
tSPH(2)
Hold Time, RTM and RFM after CLKB↑
Hold Time, RST LOW after CLKA↑ or CLKB↑(1)
Hold Time, FS0 and FS1 after RST HIGH
Hold Time, FS1/SEN HIGH after RST HIGH
0.5
–
0.5
5
–
6
0
–
0
0
–
0
–
ns
–
ns
–
ns
–
ns
tSDH(2)
tSENH(2)
Hold Time, FS0/SD after CLKA↑
Hold Time, FS1/SEN after CLKA↑
0
–
0
0
–
0
–
ns
–
ns
tSKEW1(3)
Skew Time, between CLKA↑ and CLKB↑
for OR and IR
9
–
11
–
ns
tSKEW2(3,4)
Skew Time, between CLKA↑ and CLKB↑
for AE and AF
12
–
16
–
ns
NOTES:
1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
2. Only applies when serial load method is used to program flag Offset registers.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
4. Design simulated, not tested.
7
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