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IDT72V36103

3.3 VOLT CMOS SyncFIFOTM WITH BUS-MATCHING 16,384 x 36 32,768 x 36 65,536 x 36

Integrated Device Technology 

IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH

BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36

COMMERCIAL TEMPERATURE RANGE

DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION

The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT72V3683/72V3693/72V36103 with CLKA

and CLKB set to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected

to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of IDT72V3683/72V3693/72V36103

inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.

CALCULATING POWER DISSIPATION

With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:

PT = VCC x ICC(f) + Σ(CL x VCC2 x fo)

N

where:

N

=

CL

=

fo

=

number of used outputs (36-bit (long word), 18-bit (word) or 9-bit (byte) bus size)

output capacitance load

switching frequency of an output

100

90

80

70

60

50

40

30

20

10

0

0

fdata = 1/2 fS

TA = 25°C

CL = 0 pF

VCC = 3.3V

VCC = 3.6V

VCC = 3.0V

10

20

30

40

50

60

70

80

fS  Clock Frequency  MHz

Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)

7

90

100

4678 drw 03

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