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IDT54FCT388915T150

3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE)

Integrated Device Technology 

IDT54/74FCT388915T 70/100/133/150

3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER

PIN CONFIGURATIONS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

4 3 2 1 28 27 26

FEEDBK 5

25 Q/2

REF_SEL 6

24 GND

SYNC(0) 7

VCC(AN) 8

LF 9

J28-1,

L28-1

23 Q3

22 VCC

21 Q2

GND(AN) 10

20 GND

SYNC(1) 11

19 LOCK

12 13 14 15 16 17 18

PLCC/LCC

TOP VIEW

3052 drw 02

GND 1

28 Q4

Q5 2

VCC 3

27 VCC

26 2Q

OE/RST 4

FEEDBACK 5

REF_SEL 6

SYNC(0) 7

VCC(AN) 8

LF 9

25

24

23

SO28-7 22

21

20

Q/2

GND

Q3

VCC

Q2

GND

GND(AN) 10

19 LOCK

SYNC(1) 11

FREQ_SEL 12

18 PLL_EN

17 GND

GND 13

Q0 14

16 Q1

15 VCC

SSOP

TOP VIEW

3052 drw 03

PIN DESCRIPTION

Pin Name

I/O

SYNC(0)

I

SYNC(1)

I

REF_SEL

I

FREQ_SEL

I

FEEDBACK

I

LF

I

Q0-Q4

O

Q5

O

2Q

O

Q/2

O

LOCK

O

OE/RST

I

PLL_EN

I

Description

Reference clock input.

Reference clock input.

Chooses reference between SYNC (0) & SYNC (1). (Refer to functional block diagram).

Selects between ÷ 1 and ÷ 2 frequency options. (Refer to functional block diagram).

Feedback input to phase detector.

Input for external loop filter connection.

Clock output.

Inverted clock output.

Clock output (2 x Q frequency).

Clock output (Q frequency ÷ 2).

Indicates phase lock has been achieved (HIGH when locked).

Asynchronous reset (active LOW) and output enable (active HIGH). When HIGH, outputs are

enabled. When LOW, outputs are in HIGH impedance.

Disables phase-lock for low frequency testing. (Refer to functional block diagram).

3052 tbl 01

9.8

2

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