IDT821024J Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT821024J Datasheet PDF : 13 Pages
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IDT821024 QUAD NON-PROGRAMMABLE PCM CODEC
INDUSTRIAL TEMPERATURE RANGE
TIMING CHARACTERISTICS
Clock
Parameter
t1
t2
t3
t4
t5
Description
PCLK Duty Cycle
PCLK Rise and Fall Time
MCLK Duty Cycle
MCLK Rise and Fall Time
PCLK Clock Period
Min Typ Max Units
Test Conditions
40
60
% PCLK=512kHz to 8.192MHz
25
ns PCLK=512kHz to 8.192MHz
40
60
% MCLK=2.048Hz,4.096MHz
or 8.192MHz
15
ns MCLK=2.048Hz,4.096MHz
or 8.192MHz
244
ns PCLK=512kHz to 8.192MHz
Transmit
Parameter
Description
Min
t11
Data Output Delay Time (for Short
5
Frame Sync Mode)
t12
Data Hold Time
5
t13
Data Delay to High-Z
50
t14
Frame sync Hold Time
50
t15
Frame sync High Setup Time
55
t16
TSC Enable Delay Time(for Short
5
Frame Sync Mode)
t17
TSC Disable Delay Time
50
t18
Data Output Delay Time(for Long
5
Frame Sync Mode)
t19
TSC Enable Delay Time(for Long
5
Frame Sync Mode)
t21
Receive Data Setup Time
25
t22
Receive Data Hold Time
5
Note: Timing parameter t13 is referenced to a high-impedance state.
Typ Max
70
70
220
t5+70
t5-50
80
220
t5+70
40
40
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions
MCLK
t4
t4
Figure 2. MCLK Timing
11
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