IDT821024PP Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT821024PP Datasheet PDF : 13 Pages
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IDT821024 QUAD NON-PROGRAMMABLE PCM CODEC
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Name I/O
Pin Number
PLCC
TQFP
AGND --
10
7
VCCA --
8
5
DGND --
27
30
VCCD --
25
27
DR
I
24
26
DX
O
26
28
FSR1
23
25
FSR2
FSR3
I
21
19
23
21
FSR4
17
19
FSX1
22
24
FSX2
FSX3
I
20
18
22
20
FSX4
16
18
IREF
O
9
6
VOUT1
4
43
VOUT2
VOUT3
O
7
11
2
10
VOUT4
14
13
IIN1
5
44
IIN2
IIN3
I
6
12
1
11
IIN4
13
12
MCLK
I
30
35
PCLK
I
29
34
TSC
O
28
31
A/µ
I
15
16
Description
Analog Ground.
All ground pins should be connected to the ground plane of the circuit board.
+5 V Analog Power Supply.
All power supply pins should be connected to the power plane of the circuit board.
Digital Ground.
All ground pins should be connected to the ground plane of the circuit board.
+5 V Digital Power Supply.
All power supply pins should be connected to the power plane of the circuit board.
Receive PCM Data Input.
The PCM data for Channel 1, 2, 3 and 4 is shifted serially into DR pin by the Receive Frame Sync Signal
(FSR) with MSB first. A byte of data for each channel is received every 125 µs at the PCLK rate.
Transmit PCM Data Output.
The PCM data for Channel 1, 2, 3 and 4 is shifted serially out to the DX pin by the Transmit Frame Sync Signal
(FSX) with MSB first. A byte of data for each channel is transmitted every 125 µs at the PCLK rate. DX is high
impedance between time slots.
Receive Frame Sync Input for Channel 1/2/3/4
This 8kHz signal pulse identifies the receive time slot for Channel N on a system’s receive PCM frame. It must
be synchronized to PCLK.
Transmit Frame Sync Input for Channel 1/2/3/4
This 8 kHz signal pulse identifies the transmit time slot for Channel N on a system’s transmit PCM frame. It
must be synchronized to PCLK.
Reference Current.
The IREF output is biased at the internal reference voltage. A resistor placed from IREF to ground sets the
reference current used by the analog-to-digital converter to encode the signal current present on IINn pin (n is
channel number, n = 1 to 4) into digital form.
Voice Frequency Receiver Output for Channel 1/2/3/4
This is the output of receiver amplifier for Channel N. The received digital data from DR is processed and
converted to an analog signal at this pin.
Voice Frequency Transmitter Input for Channel 1/2/3/4
This is the input to the gain setting amplifier in the transmit path for Channel N. The analog voice band voltage
signal is applied to this pin through a resistor. This input is a virtual AC ground input, which is biased at the
IREF pin.
Master Clock.
The Master Clock provides the clock for the DSP. It can be either 2.048 MHz or 4.096 MHz. The IDT821024
determines the MCLK frequency via the FSX inputs and makes the necessary internal adjustments
automatically. The MCLK frequency must be an integer multiple of the FSX frequency.
PCM Clock.
The PCM Clock shifts out the PCM data to the DX pin and shifts in PCM data from the DR pin. The PCM clock
frequency is an integer multiple of the frame sync frequency. When PCLK is connected to MCLK, the PCM
clock can generate the DSP clock as well.
Time Slot Control.
This open drain output is low active. When the PCM data is transmitted to the DX pin for any of the four
channels, this pin will be pulled low.
A/µ-Law Selection.
When this pin is low, µ-Law is selected; when this pin is high, A-Law is selected. This pin can be connected to
VCCD or DGND pin directly.
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