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IDT821064

QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE

Integrated Device Technology

IDT821064 Datasheet PDF : 33 Pages

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IDT821064 QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE

Table 2 - Time Slot Selection for Linear GCI

INDUSTRIAL TEMPERATURE RANGE

IDT821064

Channels

Time Slot

Time slot 0

Time slot 1

Time Slot

Time slot 4

Time slot 5

S1 = 0, S0= 0

Monitor

and C/I

Time Slot

Time slot 2

Time slot 3

S1 = 1, S0= 0

Monitor

and C/I

Time Slot

Time slot 6

Time slot 7

Voice

Channel

Voice

Channel

Time Slot

Time slot 2

Time slot 3

Time Slot

Time slot 6

Time slot 7

S1 = 0, S0= 1

Monitor

and C/I

Time Slot

Timeslot4

Timeslot5

S1 = 1, S0= 1

Monitor

and C/I

Time Slot

Time slot 0

Time slot 1

Voice

Channel

Voice

Channel

C/I CHANNEL

In both compressed GCI and linear GCI mode, the upstream and

downstream C/I channel bytes are continuously carrying I/O information

every frame to and from the IDT821064. In this way, the upstream processor

can have an immediate access to SLIC output data present on IDT821064’s

programmable I/O port through downstream C/I channel, as well as to

SLIC input data through upstream C/I channel. The IDT821064 transmits

or receives the C/I channel data with the Most Significant Bit first.

The MR and MX bits are used for handshaking during data exchanges

on the monitor channel.

Upstream C/I Channel

The C/I Channel which includes six C/I channel bits, is transmitted

upstream by the IDT821064 every frame. The bit definitions for the upstream

C/I channel are shown below.

Upstream C/I Octet

MSB

LSB

SI1(A) SI2(A) SB1(A) SI1(B) SI2(B) SB1(B) MR MX

The logic state of input ports SI1 and SI2 for channel A and channel B, as

well as the bidirectional port SB1 for channel A and B if SB1 is programmed

as an input, are read and transmitted in the upstream C/I channel. When

SB2 and SB3 are programmed as inputs, their data are not available in

upstream C/I channel and can be read by Global Command 9 and 10

only.

Downstream C/I Channel

The downstream C/I octet is defined as:

Downstream C/I Octet

MSB

LSB

A/B SO2 SO1 SB3 SB2 SB1 MR MX

where, A/B selects channel A or Channel B:

A/B = 0: Channel A is selected; A/B = 1: Channel B is selected.

The downstream C/I channel carries the SLIC output data bits of SO1

and SO2 for channel A or B, as well as SB1, SB2 and SB3 output bits if

SB1, SB2 and SB3 are programmed as outputs.

MONITOR CHANNEL

The monitor channel is used to read and write the internal global/local

registers and coefficient/FSK RAM of the IDT821064, or to provide SLIC

signaling. Using two monitor control bits (MR and MX) per direction,

data is transferred between the upstream and downstream devices in a

complete handshake procedure. The MR and MX bits are contained in

the C/I channel byte of the GCI frame. See Figure 3.

The monitor channel transmission operates on a pseudo-

asynchronous basis:

- Data transfer (bits) on the bus is synchronized to FSC;

- Data flow (bytes) are asynchronously controlled by the handshake

procedure.

For example: Data is placed onto the DD Monitor Channel by the

Monitor Transmitter of the master device (DD MX bit is activated and set

to ‘0’). This data transfer will be repeated within each frame (125 µs rate)

until it is acknowledged by the IDT821064 Monitor Receiver by setting

the DU MR bit to ‘0’, which is checked by the Master Transmitter of the

master device. Thus, the data rate is not 8-kbytes/sec.

Monitor Handshake

The monitor channel works in 3 states:

I. Idle state: A pair of inactive (high) MR and MX bits during two or

more consecutive frames shows an idle state on the monitor channel

and the End of Message (EOM);

II. Sending state: MX bit is activated (low) by the Monitor Transmitter,

together with data-bytes (can be changed) on the monitor channel;

III. Acknowledging: MR bit is set to active (low) by the Monitor Receiver,

together with a data byte remaining in the monitor channel.

A start of transmission is initiated by a monitor transmitter by sending

out an active MX bit together with the first byte of data to be transmitted in

the monitor channel. This state remains until the addressed monitor

receiver acknowledges the receipt of data by sending out an active low

MR bit. The data transmission is repeated each 125 µs frame (minimum

is one repetition). During this time the Monitor Transmitter keeps

evaluating the MR bit.

Flow control, means in the form of transmission delay, can only take

place when the transmitters MX and the receivers MR bit are in active

state.

Since the receiver is able to receive the monitor data at least twice (in

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