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IL145567
MCLKX
MCLKR
FSx
BCLKX
Dx
tSU(BRM)
tSU(MFB)
tH(BF)
tSU(FB)
tH(BFI)
1
2
3
4
5
6
td(ZF)
td(ZF)
td(BD)
MSB CH1 CH2
CH3 ST1
ST2
7
8
td(ZC)
9
td(ZC)
ST3 LSB
BCLKR
FSR
tH(BF)
1
tSU(FB)
2
3
4
5
6
tH(BFI)
tSU(DB)
tH(BD)
7
8
9
tH(BD)
DR
MSB
CH1
CH2
CH3 ST1
ST2
ST3 LSB
At Long Frame synchronisation, synchronisation pulses FSx or FSR should have duration not less than 3 bits
of clock generator MCLK.
Figure 4 – Time diagram at Long Frame synchronisation
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