IN74ACT174N Ver la hoja de datos (PDF) - Integral Corp.

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IN74ACT174N

HEX D FLIP-FLOP WITH COMMON CLOCK AND RESET High-Speed Silicon-Gate CMOS

Integral Corp. 

IN74ACT174

AC ELECTRICAL CHARACTERISTICS(VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=3.0 ns)

Guaranteed Limits

Symbol

Parameter

25 °C

-40°C to

Unit

85°C

Min Max Min Max

fmax Maximum Clock Frequency (Figure 1)

165

140

ns

tPLH Propagation Delay, Clock to Q (Figure 1) 1.5 10.5 1.5 11.5 ns

tPHL Propagation Delay, Clock to Q (Figure 1) 1.5 10.5 1.5 11.5 ns

tPHL Propagation Delay, Reset to Q (Figure 2) 1.5 9.5 1.5 11.0 ns

CIN Maximum Input Capacitance

4.5

4.5

pF

CPD Power Dissipation Capacitance

Typical @25°C,VCC=5.0

V

85

pF

TIMING REQUIREMENTS(VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=3.0 ns)

Guaranteed Limits

Symbol

Parameter

25 °C

-40°C to

Unit

85°C

tsu Minimum Setup Time, Data to Clock

1.5

(Figure 3)

1.5

ns

th Minimum Hold Time, Clock to Data (Figure

2.0

3)

2.0

ns

tw Minimum Pulse Width, Reset (Figure 2)

3.0

tw Minimum Pulse Width, Clock (Figure 1)

3.0

3.5

ns

3.5

ns

trec Minimum Recovery Time, Reset to Clock

0.5

(Figure 2)

0.5

ns

4

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