MH64S72QJA-7 Ver la hoja de datos (PDF) - MITSUBISHI ELECTRIC
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MH64S72QJA-7
MITSUBISHI ELECTRIC
MH64S72QJA-7 Datasheet PDF : 56 Pages
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MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Serial Presence Detect Table I
Byte
Function described
0 Defines # bytes written into serial memory at module mfgr
1
Total # bytes of SPD memory device
2
Fundamental memory type
3
# Row Addresses on this assembly
4
# Column Addresses on this assembly
5
# Module Banks on this assembly
6
Data Width of this assembly...
7
... Data Width continuation
8
Voltage interface standard of this assembly
9
SDRAM Cycletime at Max. Supported CAS Latency (CL).
Cycle time for CL=3
10
SDRAM Access from Clock
tAC for CL=3
11
DIMM Configuration type (Non-parity,Parity,ECC)
12
Refresh Rate/Type
13
SDRAM width,Primary DRAM
14
Error Checking SDRAM data width
15 Minimum Clock Delay,Back to Back Random Column Addresses
16
Burst Lengths Supported
17
# Banks on Each SDRAM device
18
CAS# Latency
19
CS# Latency
20
Write Latency
21
SDRAM Module Attributes
22
SDRAM Device Attributes:General
23
SDRAM Cycle time(2nd highest CAS latency)
-7
Cycle time for CL=2
-8
24
SDRAM Access form Clock(2nd highest CAS latency) -7
tAC for CL=2
-8
25
SDRAM Cycle time(3rd highest CAS latency)
26
SDRAM Access form Clock(3rd highest CAS latency)
27
Precharge to Active Minimum
SPD enrty data
128
256 Bytes
SDRAM
A0-A11
A0-A10
2BANK
x72
0
LVTTL
10ns
6ns
ECC
self refresh(15.625uS)
x4
x4
1
1/2/4/8/Full page
4bank
2/3
0
0
buffered,registered
Precharge All,Auto precharge
Write1/Read Burst
10ns
13ns
6ns
7ns
N/A
N/A
20ns
28
Row Active to Row Active Min.
20ns
29
RAS to CAS Delay Min
30
Active to Precharge Min
20ns
50ns
SPD DATA(hex)
80
08
04
0C
0B
02
48
00
01
A0
60
02
80
04
04
01
8F
04
06
01
01
1F
0E
A0
D0
60
70
00
00
14
14
14
32
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
4
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